Excavating
Patent
1993-01-19
1995-12-12
Voeltz, Emanuel T.
Excavating
371 26, 371 251, 371 223, 371 27, H04B 346
Patent
active
054756944
ABSTRACT:
A method of testing a digital integrated circuit for faults. A plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n are established to define a test sequence. A set of m references r.sub.1, r.sub.2, . . . , r.sub.m are predefined, corresponding to the signatures which the circuit would produce at the corresponding check points in the absence of any faults. A test sequence is applied to the circuit and an output signature s.sub.i is derived from the circuit at the corresponding check point l.sub.i. The output signature is compared with each member of the set of references. The circuit is declared "good" if the signature matches at least one member of the set of references, or "bad" if a signature matches no members of the set of references. Testing proceeds in similar fashion at the next check point, until the circuit has been tested at all check points.
REFERENCES:
patent: 4510572 (1985-04-01), Reece et al.
patent: 4768196 (1988-08-01), Jou et al.
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4855670 (1989-08-01), Green
patent: 4864570 (1989-09-01), Savaglio et al.
patent: 4897842 (1990-01-01), Herz et al.
Agarwal, V. K. and Zorian, Y., "An Introduction To An Output Data Modification Scheme," in Development In Integrated Circuit Testing, Academic Press Limited, 1987, pp. 219-256.
Bardell, P. H., McAnney, W. H. and Savir, J., Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, Inc., 1987, pp. 140-145 and 278-313.
Bhavsar, D. K. and Krishnamurthy, B., "Can We Eliminate Fault Escape in Self Testing By Polynomial Division?," Proc. Int. Test Conf., 1985, pp. 134-139.
Bhavsar, D. K., "Concatenable Polydividers: Bit-sliced LFSR Chips for Board Self-Test," Proc. Int. Test Conf., 1985, pp. 88-93.
Breuer, M. A., Gupta, R. and Lien, J., "Concurrent Control of Multiple BIT Structures", Proc. Int. Test Conf., 1988, pp. 431-442.
Gelsinger, P. P., "Built In Self Test of the 80386," Proc. ICCD, 1986, pp. 169-173.
Hassan, S. and McCluskey, E., "Increased Fault Coverage through Multiple Signatures," Proc. FTCS-14, Jun. 1984, pp. 354-359.
IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, IEEE Standards Office, N.J., May 1990, pp. 720-725.
Ivanov, A. and Pilarski, S., "Performance of Signature Analysis: a survey of bounds, exact, and heuristic algorithms," Integration, the VLSI J., 13, 1992, pp. 17-38.
Katoozi, M. and Nordsieck, A., "Built-In Testable Error Detection and Correction," IEEE J. of Solid-State Circuits, vol. 27, No. 1, Jan. 1992, pp. 59-66.
Lambidonis, D., Agarwal, V. K., Ivanov, A. and Xavier, D., "Computation of Exact Fault Coverage for Compact Testing Schemes," Proc. ISCAS, Jun. 1991, pp. 1873-1876.
Lee, Y. H. and Krishna, C. M., "Optimal Scheduling of Signature Analysis for VLSI Testing," Proc. Int. Test Conf., 1988, pp. 443-447.
Mead, C., and Conway, L., Introduction to VLSI Systems, Addison-Wesley Publishing Company, 1980.
Waicukauski, J. A., Gupta, V. P. and Patel, S. T., "Diagnosis of BIST Failures by PPSFP Simulation," Proc. Int. Test Conf., 1987, pp. 480-484.
Wu, Y. and Ivanov, A., "A Multiple Signature Scheme for BIST", Proc. Canadian Conf. on VLSI, 1991, pp. 2.2.1-2.2.7.
Wu, Y. and Ivanov, A., "A Minimal Hardware Overhead BIST Data Compaction Scheme", Proc. Int. Conf. ASIC, Rochester, N.Y., SeP. 1992.
Zorian, Y. and Agarwal, V. K., "Optimizing Error Masking in BIST by Output Data Modification", Journal of Electronic Testing: Theory and Applications, Kluwev Academic Press, 1, 59-71 (1990).
Zorian, Y., "Automated Built-In Self-Test for Embedded Macrocells," Proc. ATE and Instrumentation, Anaheim, Calif., Jan. 1991, pp. 57-62.
Scholz, H. et al., "ASIC Implementations of Boundary-Scan and BIST," Int. Custom Microelectronics Conf., London, UK, Nov. 1988, pp. 43.0-43.9.
Gelsinger, P., Iyengar, S., Krauskopf, J., and Nadir, J., "Computer Aided Design and Built-In Self-Test on the i486TM CPU," Proc. ICCD, Oct. 1989, pp. 199-201.
Wu, Y. and Ivanov, A., "A Multiple Signature Compaction Scheme for BIST," Proc. Canadian Conf. on VLSI, 1991, pp. 2.2.1-2.2.7 (also published in the Microelectronics Journal, vol. 23, 1992, pp. 205-214, Elsevier Science Publishers Ltd.).
Wu, Y. and Ivanov, A., "Minimal Hardware Multiple Signature Analysis for BIST," Proc. 11th IEEE VLSI Test Symp., Apr. 1993, pp. 17-20.
Wu, Y. and Ivanov, A., "A Fuzzy Multiple Signature Compaction Scheme for BIST," Proc. 1st Asian Test Symp., Nov. 1992, Japan, pp. 247-252.
Keller, B., Carlson, D., and Maloney, W., "The Compiled Logic Simulator," IEEE J. of Design & Test, Mar. 1991, pp. 21-34.
Keller, B. L. and Snethen, T. J., "Built-in Self-test Support in the IBM Engineering Design System," IBM J. Res. & Develop., vol. 34, No. 2/3, Mar./May 1990, pp. 406-415.
Kuban, J. R. and Bruce, W. C., "Self-Testing the Motorola MC6804P2," IEEE J. of Design & Test, May, 1984, pp. 33-41.
Li, Y. K. and Robinson, J. P., "Space Compression Methods with Output Data Modification," IEEE Trans. on CAD, vol. CAD-6, No. 2, Mar. 1987, pp. 290-294.
McAnney, W. and Savir, J., "Built-In Checking of the Correct Self-Test Signature," Proc. Int. Test Conf., 1986, pp. 54-58.
Pomeranz, I., Reddy, S. M. and Tangirala, R., "On Achieving Zero Aliasing for Modeled Faults," Proc. European Design Auto. Conf., 1992.
Agarwal, V. K., "Increasing Effectiveness of Built-In Self-Test by Output Data-Modification," Proc. IEEE 14th Symp. on Fault-Tolerant Computing, 1983, pp. 227-234.
Robinson, J. P. and Saxena, N. R., "Simultaneous Signature and Syndrome Compression," IEEE trans. CAD., May 1988, pp. 584-589.
Youn, H. Y., "Compact Testing with Intermediate Signature Analysis," Proc. 1991 IEEE VLSI Test Symposium, Apr. 1991.
Aitken, R. C. and Agarwal, V. K., "Aliasing Probability of Non-Exhaustive Randomized Syndrome Tests," Proc. Intl. Conf. CAD., 1988.
Gupta, S. K., Pradhan, D. K. and Reddy, S. M., "Zero Aliasing Compression," Proc. IEEE 20th Symp. on Fault-Tolerant Computing, 1990, pp. 254-263.
Yih, J. and Mazumder, P., "Circuit Behavior Modeling and Compact Testing Performance Evaluation," IEEE J. of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 62-66.
Ivanov Andre
Wu Yuejian
The University of British Columbia
Voeltz Emanuel T.
Wachsman Hal D.
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