Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
2007-06-12
2007-06-12
Shin, Christopher (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C710S313000, C710S104000
Reexamination Certificate
active
10456185
ABSTRACT:
One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.
REFERENCES:
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patent: 6456702 (2002-09-01), Nishihara
patent: 6590897 (2003-07-01), Lauffenburger et al.
patent: 6760852 (2004-07-01), Gulick
patent: 6797884 (2004-09-01), Kubota
patent: 6816976 (2004-11-01), Wright et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Shin Christopher
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