Fused floating-point multiply-and-accumulate unit with carry cor

Details Fused floating-point multiply-and-accumulate unit with carry cor Fused floating-point multiply-and-accumulate unit with carry cor

1996-11-18

1999-07-27

Ngo, Ohuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

059283165

ABSTRACT:
A fused floating point multiply-and-accumulate unit includes a multiplier which uses a modified Booth's algorithm to generate a sum and a carry representing a product of mantissas. An artifact of this algorithm is that the sum or carry may represent a negative value even though both mantissas are positive. The negative value may have a sign bit from sign extension or sign encoding of partial products in the multiplier. An artifact of the signed bit is a false carry out that results from canceling the sign bit. A 3-input adder simultaneously combines the sum and carry from the multiplier and performs the accumulation. The adder includes carry correction logic to suppress false carries and prevents a false carry from affecting more significant bits of the value being accumulated.

REFERENCES:
patent: 4969118 (1990-11-01), Montoye et al.
patent: 5241493 (1993-08-01), Chu et al.
patent: 5375079 (1994-12-01), Uramoto et al.
patent: 5471410 (1995-11-01), Bailey et al.
patent: 5550767 (1996-08-01), Taborn et al.
Hokenek, Erdem et al, "Second-Generation RISC Floating Point with Multiply-Add Fused", IEEE Journal of Solid-State Circuits, vol. 25, No.5, Oct. 1990, pp. 1207-1212.

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