Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-08-20
2001-07-03
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S530000, C257S209000
Reexamination Certificate
active
06255715
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates to integrated circuits and semiconductor devices. It relates particularly to a structure and method for producing integrated circuits having moisture and contamination barrier layers surrounding openings in insulating layers, such as fuse openings.
2) Description of the Prior Art
Fuses can be used to rewire memory and logic circuits. For example, in dynamic or static memory chips, defective memory cells may be replaced by blowing fuses associated with the defective cells, and activating a spare row or column of cells. This circuit rewiring using fusible links allows considerable enhanced yields and reduces the production costs. Also, logic circuits may also be repaired or reconfigured by blowing fuses. For example, it is common to initially fabricate a generic logic chip having a large number of interconnected logic gates. Then, in a final processing step, the chip is customized to perform a desired logic function by disconnecting the unnecessary logic elements by blowing the fuses that connect them to the desired circuitry. Still other applications of laser-blown fuses are possible.
An important challenge is to improve the reliability and yields of the semiconductor devices surrounding openings in insulating layers, such as openings over fusible links. A problem with openings is that moisture and other contaminants can diffuse from the openings into the device areas thus reducing circuit reliability and yields.
FIG. 1A
shows a top plan view of a semiconductor chip
82
with openings
84
through the insulating layers called fuse (cutting) openings
84
. Also, a semiconductor chip
82
sometimes contains openings over alignment marks which are used to align the laser repair machine and other tools.
A conventional fusible link region and an adjacent device region are shown in a top down view in FIG.
1
B.
FIG. 1C
shows a cross-sectional view of the same link and device regions taken along horizontal axis labeled
1
C in FIG.
1
B. Fuse
86
can be formed of a metal.
Fuse
86
is often formed over thick field oxide regions
88
in semiconductor substrate
10
as shown in
FIG. 1
c
. Fuse
86
is formed over the field oxide regions
88
to prevent shorting of the fuse
86
to the substrate
10
through a thinner insulating layer. Layers
90
,
92
,
94
, are insulating layers. Opening
84
is formed over the fuse area through the insulating layers
90
,
92
,
94
. An adjacent semiconductor device is shown with buried doped regions
100
106
, gate oxide
102
, gate
104
, via
110
and metal layers
108
,
112
. The fuse
86
is shown in
FIG. 1
c
with a hole
83
formed after the fuse was “blown” (i.e., cut or heated) by a laser. Contamination can diffuse through the hole
83
into the field oxide layer
88
and then into the other insulating layers
90
,
92
,
94
to the devices
100
,
102
,
106
.
There are two methods for blowing fuses: (a) using a laser and (b) passing a high current through the fuse. The portion of the fuse and thin insulating layer which is melted away or “blown” must not deposit or interfere with near-by devices.
A laser is often used to break the fuse forming an electrical open by heating the fuse to a high temperature. It is conventional to have an opening
84
over the fuse in the area where the fuse will be broken so that the laser heating will be more effective.
In addition, openings are often formed over alignment marks which are used to align the laser on the correct portion of the fuse to be blown. The alignment mark openings in the passivation layers are formed so that the alignment marks can be clearly viewed.
A major problem with any window opening in the passivation layers is that moisture and contamination can enter through the exposed insulation layers and diffuse to the semiconductor devices. The diffused moisture and contaminates can decrease reliability and yields. Moisture is present in the air and sodium (Na+ions) is plentiful in the environment.
As shown in
FIG. 1C
, moisture and other contaminants can enter through the hole
83
into layer
88
and diffuse to the adjacent semiconductor devices. Water will attack the metal via
110
, with the following reaction:
3H
2
O+Al→Al(OH)
3
+{fraction (3/2)}H
2
causing the resistance of metal via's
110
to increase and finally cause circuit failure. Mobile ions, such as sodium ions, can diffuse through insulating layers
90
,
92
,
94
and field oxide layer
88
. Mobile ions in the field oxide layer
88
can also cause field inversion. The field inversion causes undesired leakage current between adjacent buried doped regions
100
. Also, mobile ions in the gate oxide
102
will cause a transistor threshold shift whereby the circuit fails. Furthermore, moisture can cause the insulating layers to delaminate causing circuit failure.
The importance of overcoming the problems of moisture diffusing through fuse windows and the other various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,567,643 (Lee et al.) shows a method of forming a guard ring that uses two water impervious layers (1st and second metal layer 20 22) bonded to the silicon substrate. See FIG. 6. U.S. Pat. No. 5,538,924 (Chen) shows a guard ring composed of 2 rings (layer 16 and metal layer and a SIN barrier layer. U.S. Pat. No. 5,444,012 (Yoshizumi et al.) shows a guard ring composed of 3 layers—poly, M1 and M2. However, the M1 and M2 layers are not bonded to each other and therefore allow moisture to diffuse to the active devices. See Yoshizumi FIG. 34. Unfortunately, the problem of contaminants diffusing to the semiconductor devices through the fuse window still exists and an improved structure/method of forming a guard ring is still needed.
SUMMARY OF THE INVENTION
It is a general object of the invention to provide an improved structure and method for forming an integrated circuit moisture barrier which prevents contamination/moisture from diffusing from an opening (e.g., window) in insulating layers to device areas.
A more specific object of the present invention is to provide an improved structure and method for forming an integrated circuit moisture barrier which prevents moisture from diffusing through an opening in the insulating layers over a fuse to semiconductor devices.
In accordance with the above objects, a structure and technique for forming a moisture barrier guard ring structure for an integrated circuit on a substrate. The substrate has a fuse window area
30
and device areas
65
. The invention comprises the steps of:
a) (See
FIGS. 2
,
3
and
4
) forming an isolation region
20
over a substrate
10
having fuse window area
30
and product area
65
; the isolation region
20
covering at least the fuse window area
30
;
b) forming a fuse structure
32
33
34
over the isolation regions and across the fuse window area;
c) forming a cap layer
38
(e.g., SiN) over said substrate, said fuse structure
32
33
34
and said isolation region;
d) forming an interlevel dielectric layer (ILD)
40
over the fuse structure, isolation region
20
; and the substrate
10
surface;
e) forming a first annular ring
44
(e.g., contact w-plug) over the isolation region
20
surrounding the fuse window area
30
and over the fuse structure
32
33
34
; said first annular ring
44
forming a moisture proof seal with said cap layer
38
over said fuse structure
32
33
34
; See
FIG. 4
, area
55
;
f) forming a first conductive wiring line
48
over the first annular ring
44
;
g) forming an inter metal dielectric (IMD) layer
50
over the interlevel dielectric layer (IDL)
40
and the first conductive wiring line
48
;
h) forming a second annular ring
52
through the inter metal dielectric layer
50
on the first conductive wiring line
48
;
i) forming a second conductive w
Ackerman Stephen B.
Cao Phat X.
Chaudhuri Olik
Saile George O.
Stoffel William J.
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