Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1998-04-09
2001-05-29
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S529000
Reexamination Certificate
active
06239455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to improved fuse structure and methods for their manufacture.
2. The Relevant Technology
In order to improve yield in the manufacture of semiconductor devices, redundant circuit elements may be provided in a circuit layout. The redundant elements may be selectively connected to or disconnected from the circuit as needed to replace defective circuit elements by selectively blowing fuses in the circuit. In highly dense memory circuits, for example, spare rows and columns are formed during fabrication. If a defective bit is found during testing, a spare row or column is substituted for the defective bit by selectively blowing fuses included in the circuit for that purpose.
In state of the art memory circuit layouts, laser fuses take the form of sections of gate stacks including a polysilicon conductive layer. The stack is enclosed laterally by dielectric spacers and upwardly by a dielectric cap. A fuse is “blown” by irradiating the dielectric cap from above with laser radiation at a selected location along the gate stack. The polysilicon is heated by the laser radiation and expands, popping off the dielectric cap at the selected location, and the polysilicon is vaporized or burned off, creating a break in the conductive polysilicon layer.
Fabrication of reliable gate stack type fuses is complicated by the thickness of the overlying layers. As much as 30,000 to 40,000 Angstroms or more of overlying layers must be removed to expose the dielectric cap of the gate stack so that laser radiation may be used to blow a fuse. The overlying layers must be removed to within approximately 3000 Angstroms or less of the top of the cap in order for laser irradiation to reliably blow a selected fuse. But at etch depths as great as 30,000 or 40,000 Angstroms, variations in etch rate over the surface of a wafer, together with variations over the surface of the wafer in the layers to be etched resulting from previous process steps, can result in a difference as large as 6500 Angstroms or more between the deepest and shallowest effective depth of the etch. Etching too deep may destroy the gate stack or expose the substrate, allowing contamination and shorting. Etching not deep enough results in fuses that cannot be reliably blown.
Etching fuse openings thus typically requires painstaking control, such as a timed etch followed by an etch depth measurement for every wafer, followed by a second timed etch for a time calculated individually for each wafer. This type of control is cumbersome and time consuming. Even with control of this type, achieving an etch depth within process limits across the entire surface of a wafer is not always possible. Hence an improved method of etching fuse openings in a semiconductor device is needed.
SUMMARY AND OBJECTS OF THE INVENTION
An object of the present invention is to provide a reliable, easily performed method of etching fuse openings in a semiconductor device to etch depths within process limits.
Another object of the present invention is to provide a method for etching fuse openings in a semiconductor device providing increased uniformity of etch depth across the surface of a wafer.
Yet another object of the present invention is to provide a method for etching fuse openings in a semiconductor device providing increased uniformity of etch depth across the surface of a wafer, which method is easily integrated into standard process flows.
Still another object of the present invention is to provide a method for etching fuse openings in a semiconductor device providing increased uniformity of etch depth across the surface of a wafer, which method also provides an increase in the process limits.
Still another object of the present invention is to increase yield in the manufacture of a circuit device by providing an improved method of etching fuse openings, which method increased the number of fuses per wafer which can successfully be blown.
In accordance with one embodiment of the present invention, a silicon nitride cap and silicon nitride spacers are employed on a gate stack serving as a fuse. The etch of the fuse opening is then performed by first etching with an etch process that etches both silicon nitride and silicon oxide, then later etching with an etch process that is selective to silicon nitride. The later etch process etches the silicon nitride of the cap and spacers on the gate stack little or not at all, allowing a wider variation in etch depths without destroying the gate stack. Thus the process limits are increased, and the etch of the fuse opening is more easily kept within those limits.
In accordance with another embodiment of the present invention, a silicon nitride cap and silicon nitride spacers are employed on the gate stack serving as a fuse, and a patch is provided in the overlying layers above the gate stack serving as a fuse. The steps for etching the fuse opening are then so arranged that, at the time the patch is reached, an etch process is used that is selective to a material of the patch, resulting in an etch stop effect at the level of the patch. The etch process is then changed to an etch process that is not selective to the patch. The etch of the fuse opening is then completed with an etch process that is selective to silicon nitride so as to stop at the cap and spacers on the gate stack. In addition to allowing wider variation in etch depths by protecting the gate stack, this embodiment and variations thereof decrease the variation in the etch depth over the surface of a wafer.
Both embodiments summarized above increase the reliability of the fuse opening etch, providing increased yield and tighter, more easily maintained process control.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
REFERENCES:
patent: 4455194 (1984-06-01), Yabu et al.
patent: 4536949 (1985-08-01), Takayama et al.
patent: 5041897 (1991-08-01), Machida et al.
Becker David S.
Parekh Kunal R.
Chaudhuri Olik
Micro)n Technology, Inc.
Pham Hoai
Workman & Nydegger & Seeley
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