Fuse option for multiple logic families on the same die

Details Fuse option for multiple logic families on the same die Fuse option for multiple logic families on the same die

1999-08-31

2001-08-28

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S081000, C327S525000

Reexamination Certificate

active

06281709

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to output devices for logic circuitry, and in particular to the modification of such devices for use with multiple logic families.
BACKGROUND OF THE INVENTION
There are several families of semiconductor logic circuitry, each of which is defined at least partly by different voltage levels that they accept as input and provide as output. In addition, logic families may also specify how fast the logic needs to operate. In general, for semiconductor memories, such as Dynamic Random Access Memories, DRAMs, operating voltages are getting lower. Several factors are contributing to this lowering of voltage levels. Line widths are decreasing in size at the same time that the speeds of DRAM devices and other semiconductor devices are increasing. It is difficult to sink current into devices, with such small geometries, in order to change the voltage level. A change in voltage from high to low corresponds to a change in logic levels from or to a one or a zero. As the frequency of operation of such devices increases, such changes occur faster.
In order to change faster, the difference between the high and low voltages tends to decrease with each new logic family introduced. One such family is called Transistor-transistor Logic (TTL). The next iteration of logic produced in the TTL family is called Low Voltage TTL (LVTTL). Yet a further iteration of logic has produced the family known as Gunning Transceiver Logic (GTL). In the GTL family, more than just the voltage level has changed in order to increase the speed of operation. The output circuit for devices formed with such logic has also changed in order to obtain the increase in speed.
DRAMs for computers and other electronic devices are manufactured in very high volumes. Electronic device manufacturers design their devices to interface with such memories at various logic levels. Currently, memories are modified during their manufacturing process to provide custom input and output levels to accommodate each device's logic level requirement. This can result in differences early in the manufacturing process for memories intended for different devices. There is a need for reducing differences in the manufacturing process for each memory device with a different logic level interface. There is a further need to apply the process modifications toward the end of the manufacturing process of memory devices to better correlate manufacturing output to demand, which may change quickly. There is a further need to minimize the amount of space on a chip to accommodate input and output circuitry.
Some of the circuitry currently formed on a DRAM at the same time as the memory is being formed is shown in prior art
FIGS. 1 and 2
. In
FIG. 1
, LVTTL logic and TTL logic both use a pair of transistors or sets of transistors in parallel—a pull-up transistor
110
to pull an output line
114
up to the supply voltage
116
and a pull-down transistor
112
to pull an output line
114
down to ground depending on the logic level desired. These are very big transistors or sets of parallel transistors
110
and
112
, and require high current to switch faster. In fact, at switching frequencies above 100 MHZ, they can not switch fast enough. The pull-up transistor
110
and the pull-down transistor
112
are coupled respectively to a pull-up control
118
and pull-down control
120
, which are connected in parallel with integrated circuitry on a chip, such as a memory array
122
shown in FIG.
1
.
In comparison, as shown in
FIG. 2
, the output circuit for GTL-terminated logic uses a single transistor
224
to drive an output line
226
. The transistor
224
is a pull-down transistor
224
, driven by a pull-down control
228
. The GTL logic circuit is coupled to integrated circuitry on a chip, such as a memory array
222
shown in FIG.
2
. The GTL logic circuit requires only about one-half the current of a LVTTL or TTL output driver and hence can switch much faster.
Small Swing Transistor Logic (SSTL) logic provides for fast switching by reducing the difference between high and low output voltage levels by reducing the width of the pull-up and pull-down transistors. By decreasing the overall swing in output voltage, faster switching times are obtained.
There is a need to provide the various output levels for semiconductor devices in a manner that makes them easy to manufacture. There is a need to provide modifications of such devices late in the process of making them to ensure that the devices manufactured meet the demand for the various output levels.
SUMMARY OF THE INVENTION
Output drivers are fabricated such that a fuse option allows for selection of a desired output logic for a chip. An antifuse or a fuse, such as a laser fuse, is used for the fuse option.
In a first embodiment, Transistor-transistor Logic (TTL) family logic circuitry is manufactured on a chip for the output logic circuitry. Low Voltage TTL (LVTTL) and TTL are in the same family of logic circuitry. Thus, both require manufacture of a pull-up transistor or transistors paired with a pull-down transistor or transistors to operate as an output driver. TTL is the most common logic output family for memory chips, such as dynamic random access memory (DRAM) chips. The fuse option serves to couple the pull-up transistor either to a low reference voltage or a level translated data signal from memory chip, such that it can be activated/deactivated according to the desired output logic for a chip. The TTL default logic is easily switched to Gunning Transceiver Logic (GTL)-terminated logic by programming the fuse to turn off the pull-up transistor.
In an alternate embodiment, an antifuse is coupled to the pull-up transistor, so that the default logic of the chip is GTL-terminated. By programming the antifuse to the “on” state, the output logic of the chip is switched to TTL family logic late in the manufacturing process of DRAM or other chips. In addition, since some of the same circuitry is used in both modes, chip space is conserved.
Small Signal Transistor Logic (SSTL) is obtained by reducing the channel width of parallel coupled pull-up and pull-down transistors by programming multiple fuses, each coupled to a different pull-up and/or pull-down transistor. In this manner, much circuitry between the various optional logic output circuits is shared.
In a further embodiment, chips are manufactured such that output logic circuitry for each output logic desired is separate and complete on a chip. Logic families include TTL, SSTL, High Speed Transistor Logic (HSTL), GTL and others. The desired output logic for a chip is then selected by way of a fuse option. In this embodiment, a fuse option is coupled to either activate or shut down output circuitry as desired. After manufacturing of the chip is substantially completed, the desired output logic for a chip is selected by either blowing each fuse coupled to all but the desired output logic circuitry or programming only the antifuse coupled to the desired output logic circuitry.
This invention allows for easy selection of a chip's output logic during late stages of manufacture. This is particularly advantageous today because many different types of logic families are evolving. Since the output logic of a chip must be compatible with the input logic of an adjacent chip to properly interface the two chips, it is desirable to be able to select the output logic of a chip once the input logic of an adjacent chip is known, without requiring special manufacture or replacement of the chip having the non-compatible output logic. Valuable chip space is also conserved when manufacturing a chip in accordance with the first embodiment of the invention. Both TTL family, SSTL and GTL-terminated logic circuitry may be placed on a chip, requiring substantially only the chip space necessary to construct the TTL family logic circuitry.


REFERENCES:
patent: 4223277 (1980-09-01), Taylor et al.
patent: 4959564 (1990-09-01), Steele
patent: 5099148 (1992-03-01), McClure et al.
patent: 5107230 (1992-04-01), King
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