Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-05
2003-04-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06545308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to a sloped contact opening in a polysilicon layer, and a method for etching the sloped contact opening which is selective to oxide. More particularly, the present invention is directed to a vertically oriented capacitor formed within a sloped contact opening in a layer of polysilicon with an underlying oxide etch barrier layer, and a corresponding method for forming a vertically oriented capacitor within the sloped contact opening.
2. The Relevant Technology
Integrated circuits are being designed on an increasingly smaller scale. The smaller scale is necessary to make the integrated circuits more efficient, and aids in constructing the integrated circuits at a lower cost. These are particularly desirable characteristics in certain areas such as DRAM fabrication. One difficulty, however, in fabricating integrated circuits such as DRAM memory modules is in allocating sufficient surface area for the many capacitors that are required therein.
Traditional MOS capacitors are horizontally oriented and require a high amount of surface area. To overcome this problem, the prior art has used various forms of vertically oriented capacitors, including “stacked” capacitors. Such capacitors have a cylindrical shape with an inner plate made of a conducting material such as polysilicon, the inner plate being surrounded by a dielectric such as silicon dioxide, and an adjacent outer capacitor plate also made of a conducting material. The stacked capacitor is typically formed on a silicon substrate. A region of the substrate known as the active region is located at the bottom of the contact opening within which the vertically oriented capacitor is formed. The active region connects to the inner plate of the capacitor, which connection connects the capacitor with other semiconductor devices formed on the silicon substrate. One example of a stacked capacitor is given in U.S. Pat. No. 4,951,175 to Kei Kurosawa.
A contact opening
28
for a stacked capacitor is seen in FIG.
1
. An underlying substrate
10
has formed thereon an active region
12
, which is typically a source or drain region of a transistor. Above active region
12
is contact opening
28
formed in a polysilicon layer
26
. Two field oxide “bird's beaks” isolation regions (not shown) can be located to either side of active region
12
.
FIG. 2
is a further construction of a stacked capacitor within contact opening
28
seen in FIG.
1
. An inner capacitor plate
36
is typically formed within contact opening
28
and is intended to make electrical contact with active region
12
. A dielectric layer
37
is deposited over inner capacitor plate
36
and a outer capacitor plate
38
is deposited over dielectric layer
37
.
It is undesirable that contact opening
28
make contact with one or more bird's beak isolation regions which may be located on either side of active region
12
. It has proven difficult, however, to center contact opening
28
directly above active region
12
, especially when active region
12
is a small area. Thus, it is undesirable that inner capacitor plate
36
formed within contact opening
28
overlap one of the bird's beak isolation regions that may be on either side of active region
12
. Such an overlap may cause a leakage of the capacitor. Leakage from capacitors can cause failure in the particular circuit being formed. In the particular case where the capacitor is part of a memory cell of a DRAM memory module, a leaky capacitor will be unable to maintain charges between refresh states. This causes data corruption and thus a defect condition.
A further problem encountered with the structure of
FIG. 2
is that polysilicon layer
26
is formed as the sidewall, seen in
FIGS. 1 and 2
to be as thin as possible for greater device densities. Thus, the sidewalls of polysilicon layer
26
have a much greater dimension in the Y direction than in the X direction as seen in
FIGS. 1 and 2
. During the rigors of fabrication, the sidewalls of polysilicon layer
26
can be lifted completely off of underlying silicon substrate
10
due to their thinness. At the minimum, the sidewalls of polysilicon layer
26
can be bent or damaged. Thus, a structure with greater structural rigidity is desirable.
Accordingly, a method is needed for creating capacitors with smaller horizontal contact area to the underlying substrate. Particularly, a method is needed whereby a vertically oriented capacitor can be formed such that the capacitor can be easily located directly over an underlying active region of modest proportions without overlap into adjacent regions. Such a capacitor must also be relatively structurally rigid in order to overcome the problems discussed above.
SUMMARY AND OBJECTS OF THE INVENTION
The present invention seeks to resolve the above and other problems that have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing a contact opening in a polysilicon layer having a straight sidewall etched at a sloped angle and a method for etching such a sidewall selective to oxide which achieves each of the objects listed below.
It is an object of the present invention to provide a capacitor which occupies a minimal amount of horizontal contact area on the underlying substrate, and particularly to provide a vertically oriented capacitor which has a buried contact having minimal surface area at the substrate.
It is also an object of the present invention to provide a contact opening having a straight sidewall etched in polysilicon at a sloped angle to the substrate, wherein a vertically oriented and sloped capacitor plate can be constructed.
It is a further object of the present invention to provide a funnel-shaped capacitor having sloping capacitor plates etched in polysilicon.
It is likewise an object of the present invention to provide a method for etching sidewalls in polysilicon, which etch is selective to oxide, such that the sidewalls will not punch through an oxide etch barrier layer of the etched structure.
It is further an object of the present invention to provide such a method which can form straight sidewalls which are sloped at an angle with respect to the substrate.
It is yet another object of the present invention to provide such a method which has a high etch rate for high manufacturing throughput.
To achieve the foregoing objects in a preferred embodiment, a structure is provided for a contact opening adjacent a straight sidewall having a sloping angle with respect to a substrate, the sidewall being etched through a layer of polysilicon above an oxide etch barrier layer. The contact opening is of particular usefulness in forming capacitors, especially capacitors in DRAM memory modules. The sloped sidewall structure aids in forming a compact capacitor which allows for a greater density of memory elements within the memory module. Thus, a typical contact opening of the present invention will be etched through a polysilicon layer located on a silicon substrate which has been provided with an active region under the polysilicon layer. The active region may have one or more field oxide bird's beak isolation regions adjacent to it. Above the active region and beneath the polysilicon layer is typically located an oxide etch barrier layer. The contact opening will extend through the oxide etch barrier layer to the active region. The contact opening is bordered by the active region and the oxide etch barriers. The contact opening will preferably not contact the field oxide bird's beak isolation regions adjacent to the active region.
The present invention also provides a method for etching contact openings in polysilicon with high selectivity to oxide to form straight sidewalls in the contact opening which are set at a sloping angle with respect to the underlying substrate. The method comprises the following steps. First, a silicon substrate is provided and thereon is formed an active region, which is typically doped by ion implantation. I
Brown Kris K.
Keller David J.
Liu Louie
Hoang Quoc
Workman & Nydegger & Seeley
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