Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-28
2006-11-28
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07143377
ABSTRACT:
In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAS.
REFERENCES:
patent: 4635218 (1987-01-01), Widdoes, Jr.
patent: 5608645 (1997-03-01), Spyrou
patent: 5659716 (1997-08-01), Selvidge et al.
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6687905 (2004-02-01), Day et al.
patent: 6817001 (2004-11-01), Kudlugi et al.
patent: WO 94/06210 (1994-03-01), None
Charles Selvidge, et al., “TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation”, Virtual Machine Works, Inc., pp. 25-30 Feb. 12-14, 1995.
Jack S.N. Jean, et al., “Dynamic Reconfiguration to Support Concurrent Applications”, IEEE Transactions on Computers, vol. 48, No. 6, Jun. 1999, pp. 591-602.
Kudlugi Muralidhar R.
Selvidge Charles W.
Banner & Witcoff , Ltd.
Bowers Brandon
Chiang Jack
Mentor Graphics Corporation
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