Functional verification of logic and memory circuits with...

Details Functional verification of logic and memory circuits with... Functional verification of logic and memory circuits with...

2002-03-20

2004-11-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06817001

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to emulation of logic and memory circuits; in particular, the present invention relates to emulation of logic and memory circuits having timing signals of multiple asynchronous domains.
DISCUSSION OF THE RELATED ART
In logic circuit design, a logic emulation system is often used to verify the correct functional operation of a user design. One example of a logic emulation system is the field programmable gate array (FPGAs) based emulation system described in U.S. Pat. No. 5,596,742, entitled “Virtual Interconnections for Reconfigurable Systems,” issued on Jan. 21, 1997 (“Virtual Interconnection Patent”). The Virtual Interconnection Patent is hereby incorporated by reference in its entirety to provide background of the art.
FIG. 1
illustrates exemplary emulation system
100
for logic verification in an in-circuit emulation configuration. As shown in
FIG. 1
, emulation system
100
includes emulation hardware
5
, which consists of FPGAs
12
connected (as indicated by element
14
) in a predetermined topology (e.g., 2-dimensional mesh) and memory system
6
, host computer
2
and target system
4
. Software in host computer
2
partitions a user circuit into individual partitions, each partition to be configured into an FPGA for emulation. Typically, during emulation, a control program running in host computer
2
controls the emulation of the user circuit in emulation hardware
5
. In one form of emulation, known as “in-circuit emulation,” target system
4
provides input stimuli to, and receives output signals from emulation hardware
5
. Often, target system
4
provides one or more clock signals (“user clock signals”) to operate the user circuit implemented in emulation hardware
5
. In the system described in the Virtual Interconnection Patent, logic is evaluated and the results are communicated in emulation hardware
5
using a high-speed system clock signal (“virtual clock”). In that system, multiple signals are pin-multiplexed and pipelined between FPGAs.
In one emulation system, to ensure causality in the user circuit is reflected in the circuit configured into emulation hardware
5
, and to avoid timing problems (e.g., violation of a “hold time” requirement), signal transmission among FPGAs are scheduled in space and time. Such a scheduling scheme is described, for example, in the paper “TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation,” by Charles Selvidge et al., published in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 25-31, 1995. A system implementing the TIERS scheduling scheme is disclosed in U.S. Pat. No. 5,659,716, entitled “Pipe-lined Static Router and Scheduler for Configurable Logic System Performing Simultaneous Communications and Computation,” issued on Aug. 19, 1997 (“TIERS Scheduling Patent”). The TIERS Scheduling Patent is hereby incorporated by reference in its entirety to provide background of the art.
In the prior art, to schedule logic evaluation and the result communication among FPGAs, user clock signals are provided fixed timing relationships relative to the system clock signal, so that the user design is effectively mapped into a synchronous single clock domain. However, in modern integrated circuits, a data signal often transitions and is sampled at clock edges of multiple asynchronous clock domains. In the past, such a data signal (known as a “multiple transition and sample domain” or “MTSD” signal) could be modeled accurately with respect to only one of those constituent domains. Further, to properly operate the emulation hardware, manual and special compilation steps that isolate individual asynchronous domains in the user design are required. However, this approach is not only difficult and time-consuming, the results are often unpredictable and error-prone.
SUMMARY OF THE INVENTION
The present invention provides methods in an emulation system to correctly model and verify user circuits having logic signals (“MTSD signals”) that can transition or that are sampled in response to timing signals in more than one clock domain. The present invention can be applied to in-circuit emulation, targetless emulation, static target emulation (where the emulation provides one or more clock to the target system), co-modeling (where the model running in an emulator hardware interacts with software in the host processor), or a combination of some of the above techniques.
According to one aspect of the present invention, a method correctly transports values of an MTSD signal between a source logic module and a destination logic module by: (1) dividing the MTSD signal into related single domain signals; (2) assigning the related single domain signals to be routed through separate paths between the source and destination logic modules; and (3) causally merging the related single domain signals at the destination logic module. These logic modules can be, for example, field programmable logic arrays (FPGAs) or other programmable logic devices typically used in an emulation system. In one embodiment, the method inserts delay elements in selected paths, so that transit times in the single paths are substantially equal. In one implementation, at the destination logic module, the causal merging procedure selects as the MTSD signal value tile most recently arrived value among the values on the paths. Using these techniques, correct logic operation is ensured regardless of path delays between logic modules.
In one embodiment of the present invention, a target distance is computed. That target distance has at least the length of the longest one of separate paths. For a single domain signal between an output terminal of a source logic module and an input terminal of a destination logic module, the method ensures satisfaction of a required arrival time requirement of the single domain signal at the input terminal. The method then attempts to schedule paths of lengths less than or equal to the target distance. To facilitate scheduling of the paths, the dependency of signals between an output terminal and the input terminals that feed signal to the output terminal is traced through logic circuits within the logic module. (This method exemplifies a backward scheduling implementation; the present invention can be implemented using forward scheduling upon consideration of the principles of the present invention explained in the detail description.) The dependency relationship can be represented by a same domain depth and a multi-domain depth. To ensure proper scheduling of signals, delay elements can be inserted in the source logic module, the destination logic module, or both. The related single domain signals are dependently scheduled (e.g., scheduled together or simultaneously).
In accordance with another aspect of the present invention, a method is provided to schedule MTSD data and control signals to ensure same-domain and cross-domain timing constraints (e.g., setup and hold times) are satisfied. The problem solved involves scheduling signal arrival at a first set of input terminals of a logic module, which combinationally reach one or more data terminals of a state element, relative to a second set of input terminals of that logic module which combinationally reach one or more timing input terminals of the state element. Further, the method provides for the timing of output terminals of the logic module combinationally reached from an output terminal of the state element.
In one embodiment, a method according to the present invention includes (1) computing a minimum delay value between each of the first set of input terminals and a state element; (2) computing a maximum delay value between the second set of input terminals and the state element; (3) assigning an evaluation time for the state element; (4) assigning a required ready time at each terminal of the first set of input terminals based on the evaluation time and the minimum delay value of the terminal; and (5) assigning a ready time at each terminal of the second set of input termin

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