Functional verification of integrated circuit designs

Details Functional verification of integrated circuit designs Functional verification of integrated circuit designs

2000-07-28

2003-09-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06629296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (“target design”) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a “real environment” usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit. Speed of verification may not be as important in simulation environments as cost of implementation.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to re-designing and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high-technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
Therefore, what is needed is an efficient and cost-effective method and apparatus for the functional verification of integrated circuit designs, which can be used with complex integrated circuits.
SUMMARY OF THE INVENTION
The present invention is directed to functional verification of integrated circuit designs (“target designs”). The present invention enables functional verification to be performed quickly in a cost-effective manner. Speed is achieved by dividing a target design into combinatorial logic connecting several sequential elements (e.g., flip-flops). In turn, the combinatorial logic is divided into smaller blocks such that the corresponding truth tables can be stored in commercially available random access storage devices (RASDs). The truth tables of the divided blocks are stored in RASDs.
To generate the output data values of a target design corresponding to input data values (“primary inputs”) provided from outside, the divided blocks are evaluated using the primary inputs. Once the inputs (or values) for a block are available, evaluation typically entails a single memory access as the truth tables are pre-computed and stored in RASDs.
However, an output of a block may be used as an input by another block (“dependent block”). The dependencies are generally dictated by the target design and preserved during the division into combinatorial blocks. To preserve dependencies, a cross-connect controller (XCON) is employed. The XCON controller controls accesses to memory and provides the output data value of evaluations to the blocks requiring the value as an input.
In an embodiment, only the output values computed in a truth table are stored in RASDs. The address locations stored in RASDs are computed according to the input values from which each output value is generated. As an illustration, assuming a RASD having a four bit address line and a block (truth table) operates using four inputs, the output data value corresponding to input bits of 1011 may be stored at address location 1011. Accordingly, the address computation and retrieval can be performed without having to expend substantial time or computations.
An XCON controller along with one or more RASDs may be termed as a combinatorial logic output evaluator (CLOE). Typical implementations include several CLOEs to operate in conjunction with complex target designs. Many CLOEs are provided in a verification board and several such boards form a chassis. Many chassis may be inter-connected. In an embodiment, the XCON controllers are used for inter-CLOE communication in addition to preserving dependencies during evaluation of blocks.
RASDs can be implemented using commercially available random access memories and XCON CONTROLLERS can be implemented using integrated circuits implemented in accordance with the present invention. Accordingly, both the components can be implemented relatively cost-effectively. The other components required for providing a functional verification system can also be implemented cost-effectively. As a result, an effective functional verification system can be provided at a low cost by using the present invention.
In addition, if two blocks operate using the same inputs, the output data values of both the blocks can be stored in the same location in a different bit position such that both output data values can be retrieved in one memory access. Applying the same principle, the output data value of more than two blocks can be evaluated in one memory access by storing the output values in accordance with the storage scheme described here.
If a first block operates using a sub-set of the inputs of a second block, the output values of the first block can be replicated such that both blocks can be evaluated in a single memory access. Specifically, an output value of the first block corresponding to a set of input data values is stored in multiple locations sharing the input data values in the address. For example, assuming a four bit address and the first block operates using three inputs and the second operates using four inputs, the output of the first block corresponding to inputs
110
is stored in the locations with address
110
X (X=0 a

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