Functional verification of integrated circuit designs

Details Functional verification of integrated circuit designs Functional verification of integrated circuit designs

1998-06-15

2000-10-24

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 4, 716 1, G06F 1750

Patent

active

061382663

ABSTRACT:
A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

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