Functional pipelined virtual multiport cache memory with plural

Details Functional pipelined virtual multiport cache memory with plural Functional pipelined virtual multiport cache memory with plural

1995-07-27

1996-09-17

Kim, Matthew M.

395476, 395467, 395495, G06F 1208

Patent

active

055577687

ABSTRACT:
A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.

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