Functional module model, pipelined circuit synthesis and...

Details Functional module model, pipelined circuit synthesis and... Functional module model, pipelined circuit synthesis and...

1998-07-02

2001-09-18

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06292926

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to functional level design of an integrated circuit, and more particularly, it relates to pipelined circuit synthesis and a functional module model used in the synthesis.
A pipeline architecture is utilized for attaining a high speed operation of an electronic circuit. A method of pipelining a general circuit is described in detail in “Principles of Digital Design” (written by Gajski published by Prentice Hall).
In the pipelining, pipeline registers are inserted on signal paths, so that computation can be executed in parallel in respective areas partitioned by the pipeline registers.
FIGS.
14
(
a
) and
14
(
b
) are diagrams for illustrating the basic concept of the pipelining, wherein FIG.
14
(
a
) is a given circuit diagram and FIG.
14
(
b
) is a diagram resulting from the pipelining of the circuit of FIG.
14
(
a
). In FIGS.
14
(
a
) and
14
(
b
), a reference numeral
310
denotes a symbol model of an operator (module) and a reference numeral
320
denotes a symbol model of a pipeline operator. In FIG.
14
(
a
), positions where the pipeline registers can be inserted are positions
330
on signal paths between the operators
310
and
320
and a pipeline register insertion position
340
previously set in the pipeline operator
320
.
In FIG.
14
(
b
), four pipeline registers
350
are inserted in the circuit of FIG.
14
(
a
). Respective data data(i) through data(i+6) are successively transferred through the areas partitioned by the pipeline registers
350
in every clock period. When the delays of the areas partitioned by the pipeline registers
350
are indicated as ds
1
, ds
2
and ds
3
, respectively, the clock period of this circuit can be shortened to max(dsi), namely, the maximum value among the delays ds
1
, ds
2
and ds
3
.
When the number of pipeline steps is indicated as N, the clock period can be ideally shortened to 1/N of the initial processing time. When the number of data is indicated as M, the data can be processed in a time period as short as (M+N−1)/N of the original processing time. When M is sufficiently larger than N, the pipelining can realize an operation speed of approximately N times as high as the original speed.
However, the pipeline register insertion positions are conventionally limited to signal paths between the operators and the previously set positions in pipeline operators. Accordingly, the delays of the respective areas partitioned by the pipeline registers cannot be equalized. It is when the delays of the respective areas partitioned by the pipeline registers are equal that the clock period can be shortened to 1/N of the original processing time. However, since the delays of the areas cannot be equalized by the conventional technique, the clock period cannot be sufficiently optimized.
Furthermore, the delay and the area of each module are fixed because the layout design has already been completed. Therefore, for example, when one area partitioned by the pipeline registers has a margin in its delay against the clock period, the setting of the delay and the area size of this area cannot be changed.
In this manner, optimal pipelining has not been realized by the conventional technique.
SUMMARY OF THE INVENTION
The present invention provides a functional module model for realizing optimal pipelining and pipelined circuit synthesis using the functional module model.
Specifically, the functional module model of this invention for representing a functional module used in functional level design of an integrated circuit comprises division line data representing a division line corresponding to a position where a pipeline register can be inserted.
Preferably, the functional module model further comprises delay/area data representing a trade-off relationship between a delay and an area of each division area partitioned by the division line.
Alternatively, the method of this invention of synthesizing a pipelined circuit in functional level design of an integrated circuit on the basis of connection information of functional modules, a functional module model including division line data representing a division line corresponding to a position where a pipeline register can be inserted being used, comprising a step of selecting, in a function module for which the functional module model is prepared, whether or not to insert a pipeline register at the position represented by the division line.
Preferably, in the method of synthesizing a pipelined circuit, the functional module model includes delay/area data representing a trade-off relationship between a delay and an area of each division area partitioned by the division line, and the method further comprises a step of setting, in a functional module for which the functional module model is prepared, a delay and an area of each division area on the basis of the trade-off relationship between the delay and the area represented by the delay/area data.


REFERENCES:
patent: 5237514 (1993-08-01), Curtin
patent: 5383145 (1995-01-01), Sakiyama et al.
patent: 5519626 (1996-05-01), Culbertson
patent: 5765010 (1998-06-01), Chung et al.
patent: 5774368 (1998-06-01), Chen et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5883808 (1999-03-01), Kawarabayashi
patent: 5892682 (1999-04-01), Hasley et al.
patent: 5920485 (1999-07-01), Mangelsdorf
patent: 5926396 (1999-06-01), Ohara
patent: 01286033 (1989-11-01), None
patent: 01286034 (1989-11-01), None
J.P. Fishburn, et al., “TILOS: A Posynomial Programming Approach to Transistor Sizing”, Proc. of IEEE, pp. 326-328, 1985.
Taiwanese Office Action dated Sep. 26, 2000.

Affiliated with

Also associated with

Rating

Functional module model, pipelined circuit synthesis and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Functional module model, pipelined circuit synthesis and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Functional module model, pipelined circuit synthesis and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2517241