Functional level configuration of input-output test circuitry

Details Functional level configuration of input-output test circuitry Functional level configuration of input-output test circuitry

1999-06-03

2002-09-17

Siek, Vuthe (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06453448

ABSTRACT:

BACKGROUND
The invention relates generally to semiconductor device design and, more particularly, to the functional representation of the device's input-output test circuitry.
The design of semiconductor devices using programmable logic device (PLD), application specific integrated circuit (ASIC), and field programmable gate array (FPGA) technologies generally includes the design of input-output (I/O) circuits for each of the device's I/O ports and the test circuitry to validate operation of the I/O circuits. In one test mode, I/O test circuits coupled into a string configuration wherein the output from one test circuit is coupled to the input of the next closest test circuit. Following device fabrication, I/O test circuit strings may be used to facilitate operational testing such as, for example, determining whether an I/O circuit meets DC input and output threshold voltage requirements.
Referring to
FIG. 1
, a typical design process for an ASIC device begins with a designer's conception (block
100
), followed by the development of a functional model (block
102
). Functional models may be generated using any one of a variety of hardware description languages such as VHDL and VERILOG. Functional models may be used to exercise and/or verify the operational characteristics of the device's design via simulation tools. Once a design is thought to be complete, it may be compiled (also referred to as synthesized) into a gate level description (block
104
) that describes the device in terms of vendor-specific gates and interconnections thereto. Following compilation, the gate level description may be imported into a vendor-specific place and route tool (block
106
) that may then be used to generate a netlist (block
108
)—the electrical connectivity data associated with the specified design. Netlist data may then be used to drive fabrication and/or assembly equipment (block
110
).
Input-output circuitry is typically identified (e.g., its position within the device) and automatically interconnected during netlist generation (block
108
). At this stage in the design process, however, the information describing this interconnection is not available to functional circuit simulations which are performed on the model of block
102
. Further, it is not currently possible to extract I/O test circuit connectivity descriptions from a netlist and “insert” it into a functional model, e.g., the model of block
102
. Thus, designers are not readily able to simulate the complete device circuitry. Alternatively, it is possible to manually specify I/O test circuit interconnectivity at the functional description level (e.g., during the acts of block
102
). This technique, however, may require large amounts of a designer's time and is prone to data entry error. Consider, for example, the task of manually specifying the interconnection of 300 I/O test circuits.
Thus, it would be beneficial to provide a mechanism to automatically specify the interconnection of I/O test circuitry at the functional model level during a semiconductor design process.
SUMMARY
In one embodiment the invention provides a method of representing an electronic device having input-output ports and test circuits associated with the input-output ports. The method includes receiving a functional level description of the electronic device, determining a connectivity relationship between a first test circuit associated with a first input-output port and a second test circuit associated with a second input-output port, and generating a functional level representation of the determined connectivity relationship. Functional level descriptions include hardware description languages such as VHDL and VERILOG. Methods in accordance with the invention may be stored in any media that is readable and executable by a computer system.
In another embodiment, the invention provides a computer aided design system, that includes a processor, a storage device coupled to the processor, and a program stored on the storage device to generate a functional level representation in accordance with the previously described method.


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