Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
1998-07-08
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S040000, C326S037000
Reexamination Certificate
active
06218861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a functional block and a semiconductor integrated circuit into which a plurality of functional blocks are incorporated in combination and, more particularly, an LSI design technology using functional blocks whose delay analysis can be facilitated.
2. Description of the Related Art
In the prior art, normally system designers have architected a desired system by arranging a plurality LSI chips on a printed wiring board and then providing wiring between them. The LSI manufacturers have fabricated LSI chips for respective functions such as CPU, memory, peripheral circuit, etc.
In recent years, with the progress of miniaturization and higher density of LSI, several millions of transistors have been incorporated on one chip. Therefore, a plurality of functions have been able to be mounted on one chip. That is, the change from silicon-on-system to system-on-silicon has been brought about. In order to answer to such change to the system-on-silicon, the LSI manufacturers have kept a large number of functional blocks which are constructed in each functional unit such as CPU, peripheral circuit, etc. and also enhanced the functional blocks as a library. Such library has been assembled by preparing circuit information and layout information concerning the kept functional blocks as the database. The LSI manufacturers have implemented the LSI by using various functional blocks which are prepared in the library in combination. By employing the above library, the LSI manufacturers can take quick responses to new LSI development requests issued from the system designers respectively.
A functional block in the prior art will be explained with reference to
FIG. 1
hereinafter.
FIG. 1
shows an example of a configuration of the functional block in the prior art. A functional block
1
comprises a function portion
2
, a plurality of input terminals
3
-
1
,
3
-
2
,
3
-
3
, . . . ,
3
-m (where m is a natural number) connected to the function portion
2
, a plurality of output terminals
4
-
1
,
4
-
2
,
4
-
3
, . . . ,
4
-n (where n is a natural number), a clock input terminal
5
for receiving a clock signal CLK, and a reset input terminal
6
for receiving a reset signal RST. The function portion
2
can perform predetermined operations of a plurality of input signals IN
1
, IN
2
, IN
3
, . . . , INm supplied from the input terminals
3
-
1
,
3
-
2
, . . . ,
3
-m, and then output results of the operations from the output terminals
4
-
1
,
4
-
2
,
4
-
3
, . . . ,
4
-n as output signals OUT
1
, OUT
2
, OUT
3
, . . . , OUTn. The clock signal CLK and the reset signal RST are supplied to the function portion
2
. The clock signal CLK is a signal used as reference in carrying out a synchronous operation. The functional block
1
can perform the synchronous operation on a basis of the clock signal CLK. Regardless of its present state, the functional block
1
can be brought into its reset state by the reset signal RST.
The function portion
2
has a plurality of logic portions
7
-
1
,
7
-
2
,
7
-
3
, . . . ,
7
-k (where k is a natural number). The logic portions
7
-
1
, . . . ,
7
-k can receive at least one of plural input signals IN
1
, IN
2
, . . . , INm and generate the output signals OUT
1
, OUT
2
, . . . , OUTn respectively. In some cases, the function portion
2
has synchronizing circuits such as flip-flops, though not illustrated.
Further, the flip-flops serving as the synchronizing circuits are arranged at need on the input side and the output side of the function portion
2
. For example, in
FIG. 1
, a flip-flop
8
is arranged on the input side of the function portion
2
while a flip-flop
9
is arranged on the output side of the function portion
2
. In other words, the flip-flop
8
is connected between an input terminal
3
-
1
and a logic portion
7
-
1
while the flip-flop
9
is connected between a logic portion
7
-
2
and an output terminal
4
-
2
. A clock signal CLK input from the clock input terminal
5
is supplied to both clock terminals CK of the flip-flop
8
and the flip-flop
9
via a buffer
10
. The flip-flop
8
can receive the input signal IN
1
and then output the input signal IN
1
to the logic portion
7
-
1
in synchronous with the clock signal CLK. The flip-flop
9
can receive the output signal of the logic portion
7
-
2
and then output it to the output terminal
4
-
2
as the output signal OUT
2
in synchronous with the clock signal CLK. In addition, the reset signal RST is input into the reset terminals R of both flip-flops via a buffer
11
. Both the flip-flops
8
,
9
can be brought into their reset states by the reset signal RST irrespective of their present states.
In this way, in the functional block in the prior art, the function portion
2
can generate the output signals OUT
1
, OUT
2
, OUT
3
, . . . , OUTn in response to the input signals IN
1
, IN
2
, IN
3
, . . . , INm being input from the input terminals
3
-
1
,
3
-
2
,
3
-
3
, . . . ,
3
-m, and then output such output signals OUT
1
, OUT
2
, OUT
3
, . . . , OUTn to the output terminals
4
-
1
,
4
-
2
,
4
-
3
, . . . ,
4
-n via buffers
12
-
1
,
12
-
2
,
12
-
3
, . . . ,
12
-n respectively.
In order to manufacture the products in accordance with specifications, it is common for the LSI manufacturer to execute the function, timing and other design verifications by virtue of simulation with using a computer system before manufacture and then start actual manufacturing steps after the verifications has been completed. The verifications can be conducted based on a functional model which can be architected by combining the functional blocks together. Timing specifications for respective functional blocks have been very important in the verifications. However, in recent years, circuit configurations of respective functional blocks have become more complicated according to increases in the scale and the operational speed of the LSI, so that it has not been easy to precisely define the delay time of the output signals for the input signals of the functional blocks. As a result, the verifications based on the above simulation has become difficult.
For example, an AND-OR circuit composed of a two-input AND gate and a two-input OR gate will be explained. In this AND-OR circuit, an output of the AND gate and one input A of the OR gate are connected. Only if the output of the AND gate is 0, an output change of the OR gate depends on other input B change of the OR gate. The output of the AND gate is 0 only when a combination of the inputs of the AND gate is (0,0), (0,1), (1,0). In this OR gate, there are certain differences in delay time of the output for the input B according to the inputs of the AND gate.
Like this, the delay time of one output for one input depends on the state of others. Nevertheless, shown in
FIG. 1
, the functional block in which a number of such logic circuits has a large number of input signals. Therefore, it is very difficult in practice to define clearly the delay time. One of causes is that a plurality of signal transmission lines are present from one input to one output. The second cause is that it cannot be decided from the state of the inputs which line has been taken. The third cause is that it is decided from the output signal change which input signal has changed.
Meanwhile, the flip-flop
8
is provided between the input terminal
3
-
1
and the logic portion
7
-
1
. The input signal IN
1
is fetched into the flip-flop
8
once. The flip-flop
8
outputs the input signal IN
1
to the logic portion
7
-
1
in synchronous with the clock signal CLK. However, it is still difficult to define the delay time caused from an output Q of the flip-flop
8
to the output terminal
4
-
1
. Then, the flip-flop
9
is connected on the output side of the logic portion
7
-
2
. Hence, the logic portion
7
-
2
can output the output signal OUT
2
to the output terminal
4
-
2
in synchronous with the clock signal CLK. However, there exists no synchronizing circuit on the input
Muroga Hiroki
Shijo Takao
Sudo Fumio
Foley & Lardner
Kabushiki Kaisha Toshiba
Tokar Michael
Tran Anh
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