Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-09-14
2004-01-13
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S033000
Reexamination Certificate
active
06678841
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a function test support system, a function test support method and a hardware description model to be applied to a CAD system to support hardware design using a computer.
In function and logic design of a LSI, functions to be designed are described as a set of element operations in a language of a hardware description language (HDL), which is verified by function simulation. The function simulation is performed not only in a single form of a LSI to be designed, but also in a combined form of the above LSI with other LSI models (external models) connected to the above LSI. For example, function simulation of a bus bridge LSI connected to a CPU bus is performed according to the following steps: a CPU and external models of memories are connected; test items for functions and internal states of the LSI to be designed are set; test vectors to cover the above test items are formed; and it is verified, using the above test vectors, that operations such as memory write in and read from the CPU are correctly performed (a document “PCI Source Model User's Manual” by Synopsys,Inc. February 1999). Now, operations such as memory write and read may be correctly and easily performed, for example, by writing a description in an external model, the above description enabling expected value comparison of the read and write values to be performed at the last part of the simulation. However, “have test items set by a designer been met (tested) ?”, that is, “has a model of a LSI to be designed been made in a required state at a time in the simulation by a test vector ?” requires to trace signal values of the model to be designed, and confirm a list or waveform of the trace results after completion of the simulation (a document “ModelSim EE reference manual” by Soliton Systems Co., Ltd.). Especially, when it is impossible to confirm whether the test items have been met, unless a relationship among a plurality of signals at different items, such as a relationship of “a signal B becomes 1 within three cycles after a signal A becomes 1.” is checked, there has been a problem that the confirmation requires much labor, and errors easily occur. Moreover, when it is impossible to meet the previous test items by change in the function description during the design process, it is required to correct and/or add test vectors. Thereby, the above method to confirm the waveforms has caused a problem requiring much labor for checking the confirmation.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a function test support system and a function test support method and a hardware description model, where it is possible to confirm automatically, and reliably whether test items set by a designer have been tested by simulation; moreover, to easily detect test items made redundant and ones to be corrected after changing function descriptions; and further, to make tested test items clear, even when the function descriptions are reused.
In order to achieve the above object, the present invention is configured to have the following steps to support function tests of function descriptions where functions of an integrated circuit are described as a set of one or more element operations in a hardware description language: storing a correspondence relationship between test vectors of function simulations to verify function descriptions and test items tested according to the test vectors, and a message including at least test item names being generated during execution of function simulations and denoting that start conditions of the above test item names have been met; determining every test vector whether each test item has been tested or not, based on the above stored data; and performing report output of the determination results.
According to the present invention, the above report output showing whether test items have been tested or not may cause automatic and reliable confirmation of the results.
The present invention is configured to embed in function descriptions a statement to output a message including at least test item names, when start conditions of the test items have been met, and to store a message output by execution of the above statement.
According to the present invention, it may be possible to easily confirm whether test items have been tested or not, by use of embedded test item names in function descriptions.
Moreover, the present invention is configured to have the following steps: monitoring execution of the function simulation; installing a monitor to output messages including at least test item names, when start conditions of test items have been met; and storing messages output from the above monitor.
According to the present invention, it may be possible to easily confirm whether test items have been tested or not, by use of messages output by the above monitor after monitoring execution of function simulations.
Moreover, the present invention is configured to have the following steps to support function tests of function descriptions where functions of an integrated circuit are described as a set of one or more element operations in a hardware description language: storing messages including at least test item names and test vector names being generated during execution of the function simulation for verification of the function description and denoting that start conditions of the previously set test items have been met; determining every test vector whether each test items has been tested or not, based on the above stored data; and performing report output of the determination results.
Even in the present invention, the report output showing whether test items have been tested or not may also cause automatic and reliable confirmation of the results.
In addition, the present invention is configured to store expected value comparison results of function simulations; determine pass or fail of each test item every test vector, using the above stored data and messages; and to perform report output of the determination results.
In the present invention, it may be possible to easily confirm whether simulation results have been in a passed or failed state, considering whether test items have been met or not.
In addition, the present invention is configured to output every test vector a ratio of test items tested, or a ratio of test items not tested.
According to the present invention, it may be easily grasp the processed state of tests.
In addition, the present invention is further configured to specify a subset of test items, and to output results only for test vectors related with the above specified test items.
According to the present invention, it may be possible to obtain reports only for noticed test items.
And, the present invention is further configured to display a generated list of test items from statements included in function descriptions.
In the present invention, it may be possible to easily grasp the test items embedded in the function description.
According to the present invention, it may be possible to easily confirm whether test items have been tested or not in simulations, and, to secure automatic and reliable confirmation of the simulation results. Moreover, it may be also possible to easily detect test items made redundant, and ones to be corrected after changing function descriptions of a LSI to be designed. Further, it may be possible to make tested test items, that is, used functions and element operations, clear, even when function descriptions are reused.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5604895 (1997-02-01), Raimi
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 5920830 (1999-07-01), Hatfield et al.
patent: 5951
Kurosawa Yuuichi
Matoba Tsukasa
Nishide Koichi
Okamoto Naohiko
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Iqbal Nadeem
Kabushiki Kaisha Toshiba
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