Function clock generation circuit and D-type flip-flop equipped

Details Function clock generation circuit and D-type flip-flop equipped Function clock generation circuit and D-type flip-flop equipped

1997-04-14

1999-03-16

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 83, 326 98, 327166, 327298, H03K 1900, H03K 501, G06F 104

Patent

active

058835296

ABSTRACT:
It is to realize a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy. An input terminal D of a through latch circuit LTC11 is connected to an input line of an enable signal EN, an inversion clock input terminal G is connected to the input line of the clock signal, one input terminal of a NAND gate NAND11 is connected to an output terminal Q of a through latch circuit LTC11, the other input terminal is connected to the input terminal of the clock signal CK, and the output terminal is connected to the input terminal of an inverter INV11. Then, in the through latch circuit LTC11, the enable signal EN is sampled at the rising edge of the clock signal CK, and according to the value, the clock pulse immediately after the sampling is passed or blocked by the logical gate LGT comprising a NAND gate NAND11 and an inverter INV11.

REFERENCES:
patent: 5254888 (1993-10-01), Lee et al.
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5652536 (1997-06-01), Nookala et al.

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