Function block architecture for gate array

Details Function block architecture for gate array Function block architecture for gate array

1997-03-21

2000-01-11

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

326 40, 326 41, 326 47, 327407, G06F 738, H03K 19173

Patent

active

060140380

ABSTRACT:
A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4975601 (1990-12-01), Steele
patent: 5128559 (1992-07-01), Steele
patent: 5206184 (1993-04-01), Allen et al.
patent: 5341041 (1994-08-01), El Gamal
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5386154 (1995-01-01), Goetting et al.
patent: 5416784 (1995-05-01), Johnson
patent: 5451887 (1995-09-01), El-Avat et al.
patent: 5477165 (1995-12-01), ElAyat et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5488318 (1996-01-01), Vajapey et al.
patent: 5500608 (1996-03-01), Goetting et al.
patent: 5513190 (1996-04-01), Johnson et al.
patent: 5533032 (1996-07-01), Johnson
patent: 5570041 (1996-10-01), El-Avat et al.
patent: 5592105 (1997-01-01), Cheung et al.
Chip Express.RTM. Powerpoint Presentation, as downloaded from www.chipexpress.com on Sep. 10, 1996, pp. 1-18.
Zilinx.RTM. The Programmable Logic Data Book, Sep. 1996, pp. 13-14, 4-294-4-295, 4-11-4-17.
Brown, et al. "FPGA and CPLD Architectures: A Tutorial", IEEE Design & Test of Computers, vol. 13, No. 2, Jun. 1, 1996, pp. 42-57.
Bursky, "Efficient RAM-Based FPGAs Ease System Design", Electronic Design, Jan. 22, 1996, No. 2., pp. 53,54,58,60,62.
Brown, et al.; "FPGA and CPLD Architectures: A Tutorial" IEEE Design & Test of Computers, vol. 13, No. 2, Jun. 1, 1996.
Bursky; "Efficient RAM-Based FPGAs Ease System Design" vol. 44, No. 2, Jan. 22, 1996.

Affiliated with

Also associated with

Rating

Function block architecture for gate array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Function block architecture for gate array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Function block architecture for gate array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1465062