Fully silicided gate electrodes and method of making the same

Details Fully silicided gate electrodes and method of making the same Fully silicided gate electrodes and method of making the same

2007-11-20

2007-11-20

Jackson, Jerome (Department: 2815)

Semiconductor device manufacturing: process

Forming schottky junction

Using platinum group metal

C438S285000, C257S377000, C257S285000, C257SE21439

Reexamination Certificate

active

11460762

ABSTRACT:
The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are compatible with workfunctions that are different from conventional n+ and p+ doped poly silicon electrodes. Each device region consists of at least one Field Effect Transistor (FET) device which consists of either a polysilicon gate electrode or a fully silicided (FUSI) gate electrode. A gate electrode comprised of silicon and a Ge containing layer is used in combination with a selective removal process of the Ge containing layer. The Ge containing layer is not removed on devices with threshold voltages that are not compatible with the FUSI workfunction. Devices that are compatible with the FUSI workfunction have the Ge containing layer removed prior to the junction silicidation step. The remaining thin silicon layer of the gate electrode becomes fully silicided during the same step as the junction silicidation step.

REFERENCES:
patent: 6599831 (2003-07-01), Maszara et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 7078347 (2006-07-01), Mehrad et al.
patent: 2004/0009652 (2004-01-01), Chung
patent: 2004/0094804 (2004-05-01), Amos et al.

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