Fully silicided field effect transistors

Details Fully silicided field effect transistors Fully silicided field effect transistors

2007-05-22

2007-05-22

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S655000, C257SE21203

Reexamination Certificate

active

10905549

ABSTRACT:
Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

REFERENCES:
patent: 5981365 (1999-11-01), Cheek et al.
patent: 6423634 (2002-07-01), Wieczorek et al.
patent: 6555453 (2003-04-01), Xiang et al.
patent: 6562718 (2003-05-01), Xiang et al.

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