Fully secondary DPLL and destuffing circuit employing same

Details Fully secondary DPLL and destuffing circuit employing same Fully secondary DPLL and destuffing circuit employing same

1995-09-12

1997-02-18

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327147, 327156, 331 10, 331 18, H03D 324

Patent

active

056047746

ABSTRACT:
Each of primary and secondary random-walk filters has longer and shorter time constants. A multi-valued phase comparator generates a start signal if a phase error generated when an abrupt frequency change occurs exceeds a given value. In response to the start signal, the primary and secondary random-walk filters are set to the shorter time constants. A timer is started by the start signal, and upon elapse of a predetermined period of time, sets the primary and secondary random-walk filters to the longer time constants.

REFERENCES:
patent: 4791386 (1988-12-01), Shiga
patent: 4827225 (1989-05-01), Lee
patent: 5349309 (1994-09-01), Fujii
patent: 5399985 (1995-03-01), Awata et al.
Rokugo et al; "A Digital Phase-Locked Loop for Stuffing Synchronization Systems"; Electronics and Communications in Japan, vol. 75, No. 4, Part 1, Apr. 1992, pp. 1-12.
Nakajima et al; "Performance Improvement of DPLL with Adaptive Binary Quantized Phrase-Frequency Converter"; Electronics and Communications in Japan, vol. 73, No. 8, Part 1, Aug. 1990, pp. 56-65.
Hikawa et al; "All Digital Phase-Locked Loop with a Wide Locking Range"; Electronics and Communications in Japan, vol. 70, No. 7, Part 1, Jul. 1987 .

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