Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
1998-11-05
2003-06-10
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S082000
Reexamination Certificate
active
06577157
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit chips. More specifically, the present invention relates to input/output pins of integrated circuit chips.
Prior art semiconductor devices typically include input and output pins of semiconductor devices. Input and output pins receive and transmit electrical signals which allow the semiconductor device to communicate with other devices or systems. Semiconductor devices also include power pins that supply the integrated circuit with power. Both categories of pins are essential for the proper operation of a semiconductor device.
However, prior art input/output and power pins are typically not interchangeable. Once a pin is designated as an input, output, power or ground the pin cannot be utilized in any other manner. Recent advances have allowed a pin to operate as both an input and an output pin (also referred to as a bi-directional pin).
FIG. 1
is a schematic diagram of prior art input/output pin circuitry
100
and pad
105
of a conventional semiconductor device. Input/output circuitry
100
includes input buffer circuitry
101
, output buffer
102
and pull-up circuitry
103
.
Input buffer circuitry
101
receives electrical signals applied to pad
105
from external sources. The electrical signals are relayed to internal circuitry within the semiconductor device. Input buffer circuitry
101
normally consists of two transistors, a pull up transistor
104
and a pull down transistor
106
, that act as a buffer to improve the signal integrity of the input signal from pad
105
. When working properly, transistors
104
and
106
relay the electrical signals applied to pin
105
to the internal circuitry.
Output buffer circuitry
102
relays the electrical signals generated by internal circuitry and applies it to pad
105
. Output buffer
102
usually provides high driving current (4 mA-20 mA) to charge and discharge the large capacitance (typically 50 pf to 150 pf) of the signal trace on the printed circuit board and pin capacitance of other components. In addition, output buffer circuitry
102
provides electrostatic discharge protection (ESD) to the internal circuitry of the semiconductor device. The output of the internal circuitry is initially passed through nor gates
115
and
117
.
An output enable signal controls whether the output of the internal circuitry is transmitted to pad
105
. The output enable signal is enabled when pad
105
is configured to be an output pin. Pull up transistor
110
and pull down transistor
112
pass along the output of the internal circuitry when the output enable signal is enabled.
When pad
105
is desired to be an input pin, the output enable signal is disabled. The output of transistors
110
and
112
is at indeterminate state, typically referred to as tri-state, as is well known in the art.
During operation, if pad
105
is left to “float”, i.e. there is no supply voltage or the pin is left unconnected, a transient voltage or current pulse, otherwise referred to as noise, can cause the pull down transistor
106
and/or the pull up transistor
104
of the input buffer
101
to “turn on” such that they substantially conduct current. Both the pull up transistor
104
and the pull down transistor
106
conducting current simultaneously result in what is referred to as a crowbar current. The crowbar current flowing from VCC to VSS can be significant if a significant number of input buffers are floating at the same time. For example, a typical programmable logic device may contain 400 to 500 input buffers. If a high crowbar current is instantaneously conducted between VCC and VSS it may cause the VCC voltage to “sag” and cause the entire device to fail functionally. If the crowbar current is sustainable direct current, the device will consume more power and generate more heat.
Pull-up circuitry is often utilized in order to avoid the crowbar current effect. Pull-up circuitry
103
is typically used to drive the pin to a logical high when in tri-state. Pull-up circuitry
103
includes a transistor
122
and a resistor
120
which limits current when the pin is driven low from an exterior source. Pull-down circuitry may also be used to pull the pin low instead of high. Pull-up circuitry
103
is generally needed to avoid indeterminate signals from propagating to the internal circuitry of the semiconductor device. Such signals often times create oscillations and other spurious effects in the internal circuitry.
Generally, in this manner a pin can be used as both an input pin and an output pin, such a pin is known as an input/output (I/O) pin. However, the input/output pin cannot be used as a power or a ground pin. The lack of versatility of prior art pins reduce the versatility of semiconductor devices. Conventionally, once a pin is designated as an I/O pin it cannot be used as a power pin or a ground pin. Even in programmable logic devices the I/O pins cannot be designated as power or ground pins.
I/O pins also require, in most cases, pull-up or pull-down circuitry in order to avoid spurious conditions and harmful side effects caused by indeterminate states. Pull-up or pull-down circuitry can only drive a pin either high or low regardless of the previous state of the pin. However, often times it is desired to maintain the previous state of the pin rather than indiscriminately driving the pin high or low.
A programmable I/O pin that can also act as a power pin is, therefore, desired. Complete versatility would allow for better semiconductor devices. Additionally, a pin with memory of a previous state is also desirable.
SUMMARY OF THE INVENTION
The present inventions provide a programmable pin that may be selectively configured to operate as a signal pin or a power pin. Such a programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins according to the present inventions may also be used to provide better performance of the entire integrated circuit device and reduce noise in the pins of the integrated circuit device that are signal pins. Further, the programmable pins may also include the function of retaining the last asserted state on the pins. The ability to provide programmable pins with memory provides further functionality and flexibility in the design of integrated circuit devices.
In one embodiment of the present inventions, a programmable pin includes a pad, an output buffer, a programmable circuit, and an input buffer. The pad is coupled to the output buffer and carries a signal asserted by the output buffer or by an external source. The output buffer is coupled to the programmable circuit. The programmable circuit determines which of the many modes in which the programmable pin may operate based upon a number of control signals. The input buffer is coupled to the pad and receives the signal asserted on the pad.
The programmable pin may operate in an input pin mode, output pin mode, input/output pin mode, a ground pin mode or a power supply pin mode.
In another embodiment of the present inventions, one of the control signals may be an output signal which is provided by the programmable circuit to the output buffer. The output signal is then asserted on the pad when the mode of operation involves outputting a signal through the pad.
The programmable pin may also include a memory circuit in yet another embodiment of the present inventions. The memory circuit retains a previous state asserted on the pad until a next state is asserted on the pad.
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patent: 5850151 (1998-12-01), Cliff et al.
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Bursky, Dave, “Combination RAM/PLD Opens New Application Options”, Electronic Design, pp. 138-140, May 23, 1991.
Intel Corporation, “10 ns FLEXlogic FPGA With SRAM Option”, INTEL®,
Cheung Sammy S. Y.
Rangasayee Krishna
Altera Corporation
Beyer Weaver & Thomas LLP
Le Don
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