Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1996-09-11
1998-07-14
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438398, 438964, H01L 2100, H01L 2120
Patent
active
057803269
ABSTRACT:
The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular a static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.
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Wolf et al, Silicon Processing For the VLSI Era: Vol. 1: Process Technology, Lattice Press, pp. 189-191, Month Unknown 1986.
Dennison Charles H.
Manning Monte
Lebentritt Michael S.
Micro)n Technology, Inc.
Niebling John
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