Fully-pipelined fixed-latency communications system with a real

Details Fully-pipelined fixed-latency communications system with a real Fully-pipelined fixed-latency communications system with a real

1997-09-05

1999-09-07

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

709251, 710111, 710104, G06F 1300

Patent

active

059480890

ABSTRACT:
The present invention provides for an on-chip communications method with fully distributed control combining a fully-pipelined, fixed-latency, synchronous bus with a two-level arbitration scheme where the first level of arbitration is a framed, time-division-multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token-passing mechanism. Both the latency and the bandwidth allocation are software programmable in real-time operation of the system. The present invention also provides for a communications system where access to a shared resource is controlled by the above communications protocol. Access to and from the shared resource from the subsystem is through a bus interface module. The bus interface modules provide a level of indirection between the subsystem to be connected and the shared resource. This allows the decoupling of system performance requirements from subsystem requirements. Communication over the bus is fully memory mapped.

REFERENCES:
patent: 4979096 (1990-12-01), Ueda et al.
patent: 5414813 (1995-05-01), Shiobara
patent: 5465330 (1995-11-01), Komatsu et al.
patent: 5553245 (1996-09-01), Su et al.
patent: 5701420 (1997-12-01), Nedwek et al.
patent: 5727169 (1998-03-01), Calzi

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