Fully nickel silicided metal gate with shallow junction formed

Details Fully nickel silicided metal gate with shallow junction formed Fully nickel silicided metal gate with shallow junction formed

2002-01-29

2003-04-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming schottky junction

Using platinum group metal

C438S197000

Reexamination Certificate

active

06555453

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the art of semiconductor manufacture, and in particular to the formulation of shallow source/drain (S/D) extensions and fully silicided metal gate electrodes using metal silicide technology.
DESCRIPTION OF THE RELATED ART
At least two competing aims exist in the semiconductor fabrication industry. One aim, which is motivated by the trend toward miniaturization, is to increase device density on semiconductor chips or dice. Another aim, which is motivated by increasing demand for computing power, is increased device speed. These aims stand in tension with one another because, as feature sizes decrease, the effects of resistivity increase, which results in decreased device speed.
One source of resistivity in semiconductor circuits is the junction between doped silicon regions (such as source/drain and electrode regions) and metal connects. As device sizes decrease, resistivity rises in inverse proportion with respect junction surface areas. Thus, resistivity becomes increasingly problematic as device size decreases.
The problem of resistivity has been addressed in the semiconductor fabrication industry in part by providing metal-silicon alloy connections between semiconductors and metal connects. Such metal silicon alloys are known as metal silicides. Among the known metal silicides are aluminum silicide, cobalt silicide, titanium silicide and nickel silicide. Metal suicides not only have low resistivities in and of themselves, they also provide gradual transitions between metal connects and doped-silicon source/drain (S/D) regions and gate electrodes of MOS devices. These gradual transitions reduce junction losses, and result in MOS devices with increased speed potential.
A typical MOS device
10
having silicide regions
108
a
,
108
b
,
114
over S/D regions
18
a
,
18
b
, and gate electrode
14
, respectively, is depicted in FIG.
1
. The MOS device
10
further comprises substrate
22
, doped electrode region
104
and spacers
106
. The MOS device
10
is generally fabricated as follows. First, a precursor MOS device is provided, comprising substrate
12
, dielectric
16
, gate electrode
14
, and spacers
106
. The substrate
12
is typically single crystal silicon or doped silicon. Dielectric
16
generally comprises an insulative material such as SiO
2
or SiN. Gate electrode
14
is generally polysilicon. Spacers
106
may be an insulative material such as SiO
2
, SiON or SiN. The precursor MOS device is then subjected to light ion implantation by ion bombardment at about 1-10 KeV with a suitable dopant ion, such as As, B or BF
2
at about 10
14
to about 2×10
15
ion/cm
2
, followed by Rapid Thermal Anneal (RTA) at temperatures above 1000° C. for about 5 to about 30 seconds to form lightly doped extensions reaching under dielectric
16
. This is followed by heavy ion implantation by ion bombardment at about 30-60 KeV with a suitable dopant ion, such as P or As, at about 10
15
to about 10
16
ion/cm
2
, followed by Rapid Thermal Anneal (RTA) at about 400° C. to about 600° C., to form heavily doped regions. Together, the lightly doped extension and heavily doped regions form S/D regions
18
a
,
18
b
. As a result of the two implantation and activation steps, a doped region
104
is also formed in an upper portion of gate electrode
14
. Metal silicide regions
108
a
,
108
b
,
114
, are formed by depositing a suitable silicide-forming metal on the surface of MOS device
10
, followed by RTA, and then metal stripping to remove unreacted metal.
A typical MOS device
10
according to the prior art as depicted in
FIG. 1
provides faster operation than is available without metal silicide junctions, but it also suffers from at least the following drawbacks. The prior art device
10
suffers from gate depletion at the gate/dielectric interface. Furthermore, the prior art device
10
suffers from dopant penetration, especially boron penetration.
Conceptually, the drawbacks of gate depletion and dopant penetration could be overcome by providing a metal gate electrode. However, prior art methods of fabricating metal gate electrodes have focused on depositing, patterning, and etching metal electrodes. These methods are complicated and expensive, and other methods of forming metal gate electrodes are therefore desirable.
In concept, metal-alloy gate electrodes, such as fully silicided gate electrodes, should overcome the drawbacks of gate depletion and dopant penetration. However, it is difficult to control diffusion of dopant ions under the RTA conditions necessary to produce fully silicided gate electrodes. In fact, efforts to provide fully silicided metal electrodes, wherein extensions are made by light ion implantation and extension, have failed to produce devices having both fully silicided gate electrodes and shallow extensions having depths of less than about 500 Å. Thus, the need to keep extension depth less than about 500 Å has heretofore prevented extending silicidation methodology to provide fully metal silicided gate electrodes.
SUMMARY OF THE INVENTION
There is therefore a need in the art to provide a semiconductor device having a gate electrode that is not subject to gate electrode/gate dielectric interface depletion, and methods of fabricating such a device. There is also a need in the art to provide a semiconductor device that is not subject to dopant penetration of the gate dielectric, and methods of fabricating such a device. There is further a need in the art to provide a semiconductor device with shallow S/D extensions, having extension depths of less than about 500 Å, and methods of fabricating such a device.
These and other needs are met by embodiments according to the present invention, which provide a semiconductor device having a fully silicided gate electrode and shallow S/D extensions with extension depths of less than about 500 Å, and a method of fabricating such device, which comprises providing a precursor device comprising substrate, dielectric, spacer, and polysilicon gate electrode; overlaying the precursor device with a layer of &agr;-silicon (&agr;-Si); introducing dopant into the &agr;-Si; overlaying the &agr;-Si layer with a layer of a metal capable of forming a silicide; rapid thermal annealing to form a metal silicide layer; whereby dopant segregates from the metal silicide into the substrate; stripping off unreacted metal, metal silicide, and spacer to form a device having shallow source/drain regions; subjecting the precursor device to deep source/drain junction formation by ion implantation and rapid thermal annealing; overlaying the precursor device with a layer of metal capable of forming a silicide; and subjecting the precursor device to rapid thermal annealing to form a fully metal silicided gate electrode and metal silicide regions overlaying the active source/drain regions of the device.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6004829 (1999-12-01), Chang et al.
patent: 6303479 (2001-10-01), Snyder
patent: 6362095 (2002-03-01), Woo et al.
patent: 6368950 (2002-04-01), Xiang et al.

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