Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-29
2004-05-11
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S348000
Reexamination Certificate
active
06734501
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a fully inverted type SOI-MOSFET.
Herein, the term of “SOI-MOSFET” means a field-effect transistor that employs a silicon layer provided via an insulating layer on a substrate (this layer is referred to as a “top silicon layer”) as an active region. A gate electrode is provided on the top silicon layer via a gate oxide film. A portion that belongs to the top silicon layer and corresponds to a portion located just under the gate electrode becomes a channel region, and portions located adjacently on both sides of this channel region become a source region and a drain region. The “fully inverted type” means a type such that the channel region is inverted throughout the entire thickness (the entire region in the direction of thickness) during operation.
As well-known, there is a short-channel effect as a serious problem in accordance with developments in fine structure generally in MOSFET's (MOS type field-effect transistor) and accordingly in SOI-MOSFET's. This short-channel effect itself can be overcome by increasing the impurity concentration in the substrate. If such an arrangement is adopted, there is caused another problem that the threshold voltage rises. In contrast to this, in the fully inverted type SOI-MOSFET, the short-channel effect can be overcome without increasing the impurity concentration nor making the threshold voltage rise (Japanese Patent Laid-open Publication No. HEI 11-284201). That is, in the conventional type SOI-MOSFET shown in
FIG. 11A
, a line of electric force that has originated from a gate electrode
105
via a gate oxide film
104
terminates in a channel carriers Q
1
and ionized impurities Q
2
inside a top silicon layer
103
and terminates in impurities Q
3
inside a silicon substrate
101
through an embedded oxide film
102
. However, in the fully inverted type SOI-MOSFET shown in
FIG. 11B
, an embedded oxide film
102
A is increased in film thickness, and a top silicon layer
103
A is reduced in film thickness. Therefore, a channel region
118
that belongs to the top silicon layer
103
A and corresponds to a portion located just under the gate electrode
105
is inverted through the entire thickness (the entire region in the direction of thickness), and almost all the lines of electric force that have originated from the gate electrode
105
via the gate oxide film
104
terminate in the channel carriers Q
1
inside the top silicon layer
103
A. Therefore, in the fully inverted type SOI-MOSFET, the controllability of the channel charges by the gate electric field can be improved, and the short-channel effect can be restrained.
Describing in concrete, the SOI-MOSFET generally has the following three types of operation modes depending on the state inside the top silicon layer. The operation modes include (1) a partially depleted type such that an inversion layer, a depletion layer and a neutral region exist inside a top silicon layer similarly to the bulk MOSFET, (2) a fully depleted type such that only an inversion layer and a depletion layer exist and (3) a fully inverted type such that only an inversion layer is formed. For example, in case that the impurity concentration in the channel region is N
A
=10
17
cm
−3
, there is resulting the (1) partially depleted type when the thickness of the top silicon layer is greater than 1 &mgr;m, the (2) fully depleted type when the thickness is not smaller than 100 nm and not greater than 1 &mgr;m and the (3) fully inverted type when the thickness is not greater than 10 nm. When the impurity concentration in the channel region differs from N
A
=10
17
cm
−3
, the widths of the depletion layer and the inversion layer are varied, and therefore, the thickness of the top silicon layer that enters each operation mode is also varied. The neutral region and the depletion layer are removed by reducing the film thickness of the top silicon layer, by which the controllability of the inversion layer by the gate electric field is improved to restrain the short-channel effect. Even in the case of a MOSFET of the partially depleted type (1) having a channel length that causes the short-channel effect, the short-channel effect is restrained with the provision of the fully depleted type of (2). Furthermore, even in the case of the MOSFET of this fully depleted type having a channel length that causes the short-channel effect, the short-channel effect is restrained with the provision of the fully inverted type of (3). As described above, in the fully inverted type SOI-MOSFET, the short-channel effect is restrained to enable the threshold voltage to be easily controlled.
An effective mutual conductance G
m
during the device operation depends on not only a mutual conductance g
m
when only the channel region is taken into consideration but also a source resistance R
S
. The effective mutual conductance G
m
of the entire device is expressed as:
G
m
=g
m
/(1+
R
S
g
m
) (1)
by the mutual conductance g
m
of the channel region and the source resistance R
S
. The source resistance R
S
is expressed as:
RS~&rgr;
s
L/d
(2)
by a width d in a direction perpendicular to the channel direction of the diffusion layer, a length L in a direction that coincides with the channel direction and a sheet resistance &rgr;
s
. In the above-mentioned fully inverted type SOI-MOSFET, the top silicon layer
103
A is reduced in film thickness so that the top silicon layer
103
A is inverted throughout the entire thickness. Therefore, a source region
116
and a drain region
117
, which belong to the top silicon layer
103
A and are located adjacent to a channel region
118
, are concurrently reduced in film thickness. Therefore, in the above-mentioned fully inverted type SOI-MOSFET, the sheet resistance &rgr;
s
is increased to increase the source resistance R
S
. The increase in the source resistance R
S
cancels the increase in the mutual conductance g
m
of the channel region, and this leads to a problem that the effective mutual conductance G
m
and accordingly a current drive power is not increased in spite of the intention. According to the results of calculation carried out by the present inventors by three-dimensional device simulation, as shown in
FIG. 4
, the effective mutual conductance G
m
is rather reduced when a film thickness t
Si
of the top silicon layer is reduced to 10 nm or less, and the current drive power is consequently reduced.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a fully inverted type SOI-MOSFET capable of increasing the effective mutual conductance (G
m
).
In order to achieve the aforementioned object, the present inventors paid attention to the reduction in resistance of the source region. In the standard semiconductor processes, the source region and the drain region are formed symmetrically on both sides of the channel region. However, from the point of view of mutual conductance based on the equation (1), there is no influence exerted even when the drain resistance is made different from the source resistance. Accordingly, there is required no specific consideration for a limitation on the drain region. It is to be noted that, as a realistic approach, the following analysis is based on the case where the source region and the drain region are formed symmetrically on both sides of the channel region.
First of all, in order to reduce the resistance of the source region itself, the present inventors examined an increase in the impurity concentration of the source/drain region. According to the results of calculation carried out by the present inventors through the three-dimensional device simulation, as shown in
FIG. 5
, if the impurity concentration N
D
of the source/drain region is increased from 10
20
cm
−3
to 10
21
cm
−3
, then the effective mutual conductance Gm is increased from about 200 mS/mm to 295 mS/mm. The reason for the above is considered to be ascribed to a reduction in the source resistance R
S
as
Akagi Yoshiro
Hanajiri Tatsuro
Saito Akira
Sugano Takuo
Toyabe Toru
Landau Matthew C.
Nixon & Vanderhye P.C.
Sugano Takuo
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