Fully integrated phase-locked loop with resistor-less loop filer

Details Fully integrated phase-locked loop with resistor-less loop filer Fully integrated phase-locked loop with resistor-less loop filer

1998-04-14

2000-12-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327148, 327149, 327150, 327156, 375373, 375374, H03D 324

Patent

active

061576913

ABSTRACT:
A phase-locked loop includes a phase detector, a charge pump, a resistor-less loop filter and a voltage-controlled oscillator ("VCO"). The phase detector has a reference input, a feedback input, and a charge control output. The charge pump is coupled to the charge control output, and the resistor-less loop filter is coupled to the charge pump. The VCO has a control voltage input coupled to the resistor-less loop filter, a clock output coupled to the feedback input and a plurality of delay elements which are coupled together in series to form a ring oscillator. Each delay element includes a delay element output. A MOSFET gate oxide capacitance is coupled between each delay element output and the charge control output.

REFERENCES:
patent: 5068628 (1991-11-01), Ghoshal
patent: 5400370 (1995-03-01), Guo
patent: 5410263 (1995-04-01), Waizman
patent: 5594392 (1997-01-01), Kondoh et al.
patent: 5838204 (1998-11-01), Yao
patent: 5969552 (1999-10-01), Lee et al.
patent: 5970110 (1999-10-01), Li
Ilya I. Novof, "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and .+-.150 ps Jitter", IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995.

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