Fully hidden refresh dynamic random access memory

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S194000

Reexamination Certificate

active

06891770

ABSTRACT:
Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

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