Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar transistor
Reexamination Certificate
1999-11-24
2001-07-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Bipolar transistor
C326S112000, C326S127000
Reexamination Certificate
active
06265901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multiple input restrictive logic OR circuit and more particularly to a high speed fully differential logic OR circuit with multiple non-overlapping inputs.
2. Description of the Related Art
When designing systems such as automated test equipment it is desirable to provide a high speed logic circuit which accepts numerous inputs and provides a single output, where only one input at a time is active and the output is active when one of the inputs is active. In such high speed applications, input-to-output propagation delays must be minimized while remaining uniform for each input. It is also desirable to minimize signal noise and interaction between circuit devices that may degrade the signal.
Differential logic OR circuits have been developed using known ECL technology such as the differential two input Motorola MC10EL05. However, these circuits commonly have only 2 or 3 inputs which suffer from different input-to-output propagation delays. In addition, to construct a logic OR circuit with more inputs, for example 8, several 2 or 3 input OR circuits must be coupled together in a tree structure. Such tree structures have different input to output propagation delays for the different inputs depending on the path taken through the logic tree. They also result in undesirable interaction between the multiple logic gates, which can degrade the signals.
A multi-input logic OR circuit could also be implemented with a “Wired-OR” circuit, in which single-ended input lines are combined to produce an “OR” output. An example of this approach is embodied in the Motorola MECL 10K 4 input wired-OR logic gate. This circuit has relatively low propagation delay and is generally symmetric with respect to propagation delay between input and output. However, its single-ended inputs make the circuit susceptible to jitter and makes propagation delay sensitive to environmental changes.
A multi-input logic OR circuit could also be implemented with a multiplexer that selects data from one of the multiple input lines and directs the data to a single output line. An example of this approach is embodied in the Motorola MC10H164 8-line multiplexer. The selected input line is activated by control lines and the number of control lines increases as the number of inputs increase. A four input multiplexer requires two control lines, while an eight input multiplexer requires three control lines. These circuits suffer from undesirable input-to-output propagation delays and experience an additional delay in the settling time of the control lines. The necessity for control lines makes this approach significantly more complex.
SUMMARY OF THE INVENTION
The present invention is a superior method and device for providing a high speed restrictive logic OR function with multiple fully differential inputs, for use in applications where only one of the multiple inputs is active at one time. The circuit inputs experience very small input-to-output propagation delays, with each of the inputs seeing the same propagation delay. The differential inputs minimize jitter and provide for a small transition time during which the inputs change states from active to inactive or vice versa. The invention also provides a differential output, eliminating the need for associated invert functions at the output. The circuit is implemented without the need for control lines.
The new logic circuit accepts multiple differential inputs, each comprising an input signal and its complement. At the input circuit, the differential input voltage signals are converted to respective differential current signals. The differential currents from the differential voltage inputs are then coupled to an output circuit which indicates whether one of the inputs is active.
Any active input signal is converted to an active current unit and any active complement input signal is converted to a complement current unit of equal magnitude. The complement current units are summed together and an opposing current of (N−1) current units subtracted from the sum, where N is the total number of inputs. The difference, which is equal to zero if none of the input signals is active and to one current unit if one of the input signals is active. The output currents are preferably converted to an output differential voltage that produces an active output when one of the inputs is active, and a complemented output when none of the inputs is active.
To enhance the invention's accuracy and reduce the potential for mismatches between different paths, a common reference current can be used to derive both the opposing current of (N−1) current units and the active and complemented differential transistor currents. This ensures that the opposing current closely matches the summed complement currents when one of the inputs is active. Specifically, if an input is active the summed complement currents will be (N−1)current units. Using the same unit reference current for the opposing current of (N−1) current units results in a net zero output current.
REFERENCES:
patent: 5668495 (1997-09-01), Vora et al.
patent: 6093981 (2000-07-01), Cali' et al.
patent: 6137340 (2000-10-01), Goodell et al.
Data Sheet for Motorola Part No. ML10EL05, (1996).
Data Sheet for Motorola Part No. MECL 10K (1996).
Data Sheet for Motorola Part No. MC10H164 (1996) 8-Line.
DiTommaso Vincenzo
Stern Kenneth J.
Analog Devices Inc.
Koppel & Jacobs
Tokar Michael
Tran Anh
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