Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-24
2001-09-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C254S288000, C254S260000, C254S347000, C254S352000
Reexamination Certificate
active
06291845
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present inventions relate to integrated circuit devices and processes, and particularly to CMOS devices and processes which are highly resistant to latchup.
Latchup
Latchup is one of the basic problems of CMOS technology. Consider the sequence of a PMOS source region, the surrounding N-well region, a p-well region (or p-type epitaxial layer), and an NMOS source region. This sequence of regions will inevitably occur in normal bulk CMOS designs, and it defines a thyristor. This thyristor is referred to as “parasitic,” since it is not created intentionally. A thyristor is a bipolar device which has an extremely low on-resistance. Once the thyristor turns on (or “fires”), it will remain on for as long as it can draw its minimum holding current. This behavior is extremely undesirable in integrated circuits, since when such a parasitic thyristor fires it may destroy the integrated circuit (by drawing excessive current), or may rapidly discharge a portable system's battery, or may simply cause the chip to remain in a “stuck” condition, and hence become unusable, until the power supply is disconnected.
Any thyristor can be regarded as a merger of a PNP transistor with an NPN transistor, and this model is frequently a convenient way to analyze the properties of the parasitic thyristor. The gain of the parasitic thyristor is equal to the product of the gains of the bipolar transistors, so degrading the gain of either parasitic bipolar helps to degrade the parasitic thyristor. (Although the thyristor reaches low impedance once triggered, it is still useful to analyze the small-signal “gain” of the thyristor in considering triggering: lower gain will mean that a larger input energy is required to trigger the thyristor. Since voltage transients are always present, it is desirable to provide some margin of immunity against triggering by transients.) There are several ways to approach the device-level properties of the thyristor: either the holding current can be increased, or the firing voltage can be increased, or the gain of one or both of the parasitic bipolar transistors can be degraded, or low-resistance shunting elements can be added to bypass one or both of the parasitic bipolar transistors (so that the current driven by one transistor does not all appear as base current on the other).
Punchthrough
Another of the basic problems in normal CMOS (or almost any other field-effect transistor formed in bulk material) is punchthrough: when the depletion regions around the source/drain boundaries spread sufficiently to touch, then current can bypass the channel region, i.e. the source and drain are essentially shorted together.
Thin Film Transistors and Full Dielectric Isolation
An old goal in MOS processing has been to manufacture transistors which are separated from each other by dielectric layers, and not merely by reverse-biased junctions. However, this is not easy to achieve.
One way to obtain some of the advantages of full dielectric isolation is with thin-film transistors. Such transistors are fabricated with their channel regions in a deposited thin film layer (typically polycrystalline Si or SiGe). Thin-film transistors do provide full dielectric isolation, but they typically suffer from low mobilities and high junction leakage currents.
SOI and SIMOX
It has long been realized that silicon-on-insulator (SOI) structures, in which a layer of monocrystalline silicon overlies a layer of an insulator, would permit full dielectric isolation. Since the 1970s various techniques have been proposed for SOI, and many successful results have been published, but none of these techniques have remained in production use. (The nearest approach was the silicon-on-sapphire technology which was aggressively promoted by RCA.)
However, a new approach which was developed in the 1980s has begun to see mass production in the mid-1990s. This is the “SIMOX” approach, which uses high-dose oxygen implantation (followed by a significant anneal) to form a buried silicon dioxide layer under silicon which is still monocrystalline. Many articles have shown how to practice this process; see e.g. Isilkawa et al., “Formation mechanisms of dislocation and Si island in low-energy SIMOX,” B91 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 520 (1994); Li et al., effects of dose and target temperature on low energy SIMOX layers,” 140 J. ELECTROCHEMICAL SOCIETY 1780 (1993); Nejim et al., “Direct formation of device worthy thin film SIMOX structures by low energy oxygen implantation,” B80-81 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 822 (1993); Li et al., “The effects of dose and target temperature on low energy SINFOX layers,” PROCEEDINGS OF THE FIFTH INTERNATIONAL SYMPOSIUM ON SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES 368 (1992); Reimbold et al., “Aging analysis of nMOS of a 1.3-&mgr;m partially depleted SIMOX SOI technology comparison with a 1.3-&mgr;m bulk technology,” 40 IEEE TRANS'NS ELECTRON DEVICES 364 (1993); Usami et al., “Evaluation of bonding silicon-on-insulator films with deep-level transient spectroscopy measurements,” E75-C IEICE TRANS'NS ELECTRONICS 1049 (1992); Takao et al., “Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET,” 39 IEEE TRANS'NS ELECTRON DEVICES 2147 (1992); Nakashima et al., “Buried oxide layers formed by low-dose oxygen implantation,”
7
J. MATERIALS RESEARCH 788 (1992); Barklie et al., “E′
1
centres in buried oxide layers formed by oxygen ion implantation into silicon,” B65 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 93 (1992); Bae et al., “The effects of annealing conditions on the characteristics of SIMOX SOI,” 28A J. KOREAN INSTITUTE OF TELEMATICS AND ELECTRONICS 54 (1991); Visitserngtrakul et al., “Mechanisms of defect formation and evolution in oxygen implanted silicon-on-insulator material,” in MICROSCOPY OF SEMICONDUCTING MATERIALS 1989 at 557; Lacquet et al., “Ultraviolet reflectance of room temperatures nitrogen implanted silicon (SOI),” 1989 IEEE SOS/SOI TECHNOLOGY CONFERENCE at 110; Fechner et al.; “Physical characterization of low defect SIMOX materials,” 1989 IEEE SOS/SOI TECHNOLOGY CONFERENCE at 70; De Veirman et al., “Defects in high-dose oxygen implanted silicon,” 38-41 MATERIALS SCIENCE FORUM 207 (1989); Cristoloveanu, “Electrical evaluation of SIMOX material and integrated devices,” in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 335 (ed. Sturm et al. 1988); Scanlon et al. “Evidence for oxygen concentration changes induced by low-temperature 0-18 implantation into a SIMOX buried-oxide layer,” in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 141 (ed. Sturm et al. 1988); de Veirman et al., “HVEM and electrical characterisation of SIMOX structures,” in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 129 (ed. Sturm et al. 1988); Nieh et al., “Formation of buried oxide in MeV oxygen implanted silicon,” in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 73 (ed. Sturm et al. 1988); Sioshansi et al., “Processing SIMOX wafer below the critical temperature,” in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 67 (ed. Sturm et al. 1988); Stoemenas, “Silicon on Insulator Obtained by High Dose Oxygen Implantation, Microstructure, and Formation Mechanism,” 142 J. ELECTROCHEM. SOC. 1248 (1995); and Auberton-Hervé et al., “SOI substrates for low-power LSIs,” SOLID-STATE TECHNOLOGY, March 1995, at 87. All of these publications, and all of the references cited in them, are hereby expressly incorporated by reference. Note that some of this work has shown that implantation of nitrogen rather than oxygen can be used to form the buried dielectric layer.
Innovative CMOS Device and Process
One of the basic goals in the fabrication of thin film MOS transistors is to obtain the performance of MOS transistors that have been fabricated in single crystal silicon together with device-to-device isolation. The disclosed innovations allow the fabrication of dielectrically isolated thin film MOS transi
Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
Lee Eddie
Ortiz Edgardo
LandOfFree
Fully-dielectric-isolated FET technology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fully-dielectric-isolated FET technology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully-dielectric-isolated FET technology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2445763