Fully compensated emitter coupled logic gate

Details Fully compensated emitter coupled logic gate Fully compensated emitter coupled logic gate

1974-09-03

1976-03-23

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 330 30D, H03K 1908

Patent

active

039462463

ABSTRACT:
A circuit for minimizing voltage excursions on the emitter-follower output terminals of an emitter coupled logic (ECL) gate including a compensating circuit connected to collector nodes associated with the input switching transistors and the reference switching transistor. The compensating circuit comprises a single current source for continuously delivering current which is selectively applied in predetermined amounts to one of the collector nodes residing in a high state. This predetermined amount of current compensates for undesired voltage changes experienced at the load impedance connected to that node due to varying ambient temperatures effecting the base-emitter junction of the output emitter follower transistor.

REFERENCES:
patent: 3590274 (1971-06-01), Marley
patent: 3758791 (1973-09-01), Taniguchi et al.
patent: 3806736 (1974-04-01), Wilhelm

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