Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-01-19
2010-10-12
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S710000, C365S201000
Reexamination Certificate
active
07814382
ABSTRACT:
A memory module comprises first memory that includes memory blocks, second memory, and non-volatile memory. A control module, during testing of at least one of the memory blocks having a first address, stores data from the at least one of the memory blocks in the second memory at a second address and stores the first and second addresses in the non-volatile memory. Content addressable memory (CAM) stores addresses of defective memory locations in the first memory and stores and retrieves data for the defective memory locations.
REFERENCES:
patent: 4205301 (1980-05-01), Hisazawa
patent: 4901360 (1990-02-01), Shu et al.
patent: 4903268 (1990-02-01), Hidaka et al.
patent: 5056095 (1991-10-01), Horiguchi et al.
patent: 5127014 (1992-06-01), Raynham
patent: 5475825 (1995-12-01), Yonezawa et al.
patent: 5485595 (1996-01-01), Assar et al.
patent: 5491703 (1996-02-01), Barnaby et al.
patent: 5513135 (1996-04-01), Dell et al.
patent: 5535226 (1996-07-01), Drake et al.
patent: 5636354 (1997-06-01), Lear
patent: 5758056 (1998-05-01), Barr
patent: 5796758 (1998-08-01), Levitan
patent: 5848076 (1998-12-01), Yoshimura
patent: 5958068 (1999-09-01), Arimilli et al.
patent: 5958079 (1999-09-01), Yoshimura
patent: 5959914 (1999-09-01), Gates et al.
patent: 5973949 (1999-10-01), Kramer et al.
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6041422 (2000-03-01), Deas
patent: 6058047 (2000-05-01), Kikuchi
patent: 6065141 (2000-05-01), Kitagawa
patent: 6067656 (2000-05-01), Rusu et al.
patent: 6085334 (2000-07-01), Giles et al.
patent: 6134631 (2000-10-01), Jennings
patent: 6175941 (2001-01-01), Poeppelman et al.
patent: 6233646 (2001-05-01), Hahm
patent: 6237116 (2001-05-01), Fazel et al.
patent: 6275406 (2001-08-01), Gibson et al.
patent: 6295617 (2001-09-01), Sonobe
patent: 6385071 (2002-05-01), Chai et al.
patent: 6414876 (2002-07-01), Harari et al.
patent: 6438726 (2002-08-01), Walters, Jr.
patent: 6457154 (2002-09-01), Chen et al.
patent: 6484271 (2002-11-01), Gray
patent: 6563754 (2003-05-01), Lien et al.
patent: 6700827 (2004-03-01), Lien et al.
patent: 6751755 (2004-06-01), Sywyk et al.
patent: 6778457 (2004-08-01), Burgan
patent: 6799246 (2004-09-01), Wise et al.
patent: 6898140 (2005-05-01), Leung et al.
patent: 7017089 (2006-03-01), Huse
patent: 7051151 (2006-05-01), Perego et al.
patent: 7062597 (2006-06-01), Perego et al.
patent: 7065622 (2006-06-01), Donnelly et al.
patent: 7073099 (2006-07-01), Sutardja et al.
patent: 7216284 (2007-05-01), Hsu et al.
patent: 7308530 (2007-12-01), Armstrong et al.
patent: 2001/0048625 (2001-12-01), Patti et al.
patent: 2004/0218439 (2004-11-01), Harrand et al.
patent: 2004/0243886 (2004-12-01), Klein
patent: 2006/0158950 (2006-07-01), Klein
patent: 2008/0307301 (2008-12-01), Decker et al.
“Functional testing of content-addressable memories” by Lin et al. This paper appears in: Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on Publication Date: Aug. 24-25, 1998 On pp. 70-75 ISBN: 0-8186-8494-1 Inspec Accession No. 6142197.
“Testing and diagnosing embedded content addressable memories” by Li et al. This paper appears in: VLSI Test Symposium, 2002. Proceedings 20th IEEE Publication Date: Apr. 28-May 2, 2002 On pp. 389-394 ISBN: 0-7695-1570-3 Inspec Accession No. 7361019.
“Fully-parallel multi-megabit integrated CAM/RAM design” by Schultz et al. This paper appears in: Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on Publication Date: Aug. 8-9, 1994 on pp. 46-51 ISBN: 0-8186-6245-X Inspec Accession No. 4933182.
“Fault-tolerant content addressable memory” by Lo, J.-C. This paper appears in: Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on Publication Date: Oct. 3-6, 1993 On pp. 193-196 ISBN: 0-8186-4230-0 Inspec Accession No. 4955866.
“Memory Built-in Self-repair Using Redundant Words” Schober et al. International Test Conference Proceedings. Publication Date: Oct. 30-Nov. 1, 2001 pp. 995-1001 Inspec Accession No. 7211400.
IBM TDB NN85112562 “System for Efficiently Using Spare Memory Components for Defect Corrections Employing Content-Addressable Memory” Date: Nov. 1, 1985.
“FBDIMM—Unleashing Server Memory Capacity”; Micron Technology, Inc.; 2006; 2 pages.
Bigger, Better, Faster . . . Improve server performance with Crucial fully buffered DIMMs; Andy Heidelberg of Crucial Technology; 6 pages.
Notification of Transmittal of The International Search Report and The Written Opinion of The International Searching Authority, or The Declaration dated May 27, 2008 in reference to PCT/US2007/016661 (21 pgs).
McAuley et al. “A Self-Testing Reconfigurable CAM.” Solid-State Circuits, IEEE Journal vol. 26. Issue 3 (Mar. 1991): 257-261.
Noghani et al. “Design Rule Centering for Row Redundant Content Addressable Memories.” Defect and Fault Tolerance in VLSI Systems, Proceedings., 1992 IEEE International Workshop (Nov. 4-6, 1992): pp. 217-226.
Youngs et al. “Mapping and Repairing Embedded-Memory Defects.” Design & Test Computers, IEEE vol. 14. Issue 1 (Jan.-Mar. 1997): pp. 18-24.
Azimi Saeed
Sutardja Sehat
Britt Cynthia
Marvell World Trade Ltd.
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