Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-01-27
2001-11-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C326S058000, C370S274000, C370S279000, C375S211000
Reexamination Certificate
active
06313663
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to repeater circuits for high resistance and/or high capacitance signal lines on an integrated circuit. More particularly, the present invention relates to full swing voltage repeaters which, when employed on a high resistance and/or high capacitance bi-directional signal line facilitate propagation of signals in both directions while significantly reducing the signal propagation delay and/or signal degradation.
In some integrated circuits, there exist signal lines that span long distances and/or are coupled to many circuits. In modern dynamic random access memory circuits, for example, certain unidirectional signal lines such as address lines may be coupled to many circuits and may therefore have a high capacitive load and/or resistance associated therewith. Likewise, certain bi-directional lines such as read write data (RWD) lines may also be coupled to many circuits and may therefore also have a high capacitive load and/or resistance associated therewith. The problem of high capacitive load and/or resistance also arises for many signal lines in modern microprocessors, digital signal processors, or the like. By way of example, the same issue may be seen with loaded read data lines and write data lines of memory circuits, clock lines of an integrated circuit, command lines, and/or any loaded signal carrying conductor of an integrated circuit. The propagation delay times for these signal lines, if left unremedied, may be unduly high for optimal circuit performance.
To facilitate discussion,
FIG. 1
illustrates an exemplary signal line
100
, representing a signal conductor that may be found in a typical integrated circuit. Signal line
100
includes resistors
102
and
104
, representing the distributed resistance associated with signal line
100
. Resistors
102
and
104
have values that vary with, among others, the length of signal line
100
. There are also shown capacitors
106
and
108
, representing the distributed capacitance loads associated with the wire or signal bus and the circuits coupled to signal line
100
.
The resistance and capacitance associated with signal line
100
contribute significantly to a signal propagation delay between an input
110
and an output
112
. As discussed in a reference entitled “Principles of CMOS VLSI design: A Systems Perspective” by Neil Weste and Kamran Eshraghian, 2nd ed. (1992), the propagation delay of a typical signal line may be approximately represented by the equation
t
delay
=0.7(
RC
)(
n
)(
n+
1)/2 Eq. 1
wherein n equals the number of sections, R equals the resistance value, C equals the capacitance value. For the signal line of
FIG. 1
, the propagation delay is therefore approximately 2.1 RC (for n=2).
If the resistance value (R) and/or the capacitance value (C) is high, the propagation delay with signal line
100
may be significantly large and may unduly affect the performance of the integrated circuit on which signal line
100
is implemented. For this reason, repeaters are often employed in such signal lines to reduce the propagation delay.
FIG. 2
depicts a signal line
200
, representing a signal line having thereon a unidirectional repeater to reduce its propagation delay for signals travelling from left to right. Signal line
200
is essentially signal line
100
of
FIG. 1
with the addition of a repeater
202
disposed between an input
210
and an output
212
. In the example of
FIG. 2
, unidirectional repeater
202
is implemented by a pair of cascaded CMOS inverter gates
204
and
206
as shown. For ease of discussion, unidirectional repeater
202
is disposed such that it essentially halves the distributed resistance and capacitance of unidirectional signal line
200
.
In this case, the application of Eq. 1 yields a propagation delay of 0.7 (RC)+t
DPS
+t
DPS
+0.7 (RC) or 1.4 (RC)+2t
DPS
, wherein t
DPS
represents the time delay per inverter stage. Since t
DPS
may be made very small (e.g., typically 150 ps or less in most cases), the use of unidirectional repeater
202
substantially reduces the propagation delay of the signals traveling from node
210
to
212
(from left to right) on the unidirectional signal line
200
, particularly when the delay associated with the value of R and/or C is relatively large compared to the value of t
DPS
.
The use of unidirectional repeaters such as
202
prove to be useful in reducing the propagation delay on unidirectional signal lines where signals need to propagate only in one direction. A unidirectional repeater, however, fails to function on a bi-directional line where signals need to propagate in both directions between two given nodes. Bi-directional signal lines are required for application such as bi-directional read write (RWD) of dynamic random access memory integrated circuits ( DRAM Ics). Moreover, a bi-directional repeater would be very beneficial for bi-directional applications such as RWD lines because of the long propagation delay typically associated with these applications.
One major difficulty associated with implementation of a bi-directional repeater relates to the problem of timing the propagation of signals. This difficulty is even more problematic for applications such as bi-directional RWD where signals typically have to propagate a long distance in a chip. In such applications, the proper timing of enable control signals to allow proper propagation of signals in both directions is essential. For example, these enable control signals would be enable read and enable write control signals for bi-directional RWD applications.
As can be appreciated from the foregoing, there is a desire for techniques for implementing bi-directional full swing voltage repeaters on the high resistance and/or high capacitance bidirectional signal lines of an integrated circuit.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line. The second full-swing unidirectional repeater circuit is configured to pass a second full swing signal from the second portion of the signal line to the first portion of the signal line when the second enable signal is enabled, wherein the first full-swing unidirectional repeater circuit and the second full-swing unidirectional repeater circuit are tri-stated when both the first enable signal and the second enable signal are disabled.
In another embodiment, the invention relates to a memory integrated circuit having therein a bidirectional full swing voltage repeater implemented on a bidirectional data signal line. The memory integrated circuit includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the bidirectional data signal line and a second portion of the bidirectional data signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the bidirectional data signal line to the second portion of the bidirectional data signal line when the first enable signal is enabled. There is included a second full-swing unidirectional repeater circuit coupled between the first portion of the bidirectional data signal line and the
Hanson David R.
Mueller Gerhard
Braden Stanton C.
Infineon - Technologies AG
Tan Vibol
Tokar Michael
LandOfFree
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