Full-speed BIST controller for testing embedded synchronous...

Details Full-speed BIST controller for testing embedded synchronous... Full-speed BIST controller for testing embedded synchronous...

2001-03-05

2004-12-07

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S744000

Reexamination Certificate

active

06829728

ABSTRACT:

TECHNICAL FIELD
This invention generally relates to built-in self testing of electronic circuits, and more particularly relates to built-in self testing of embedded synchronous memories within an integrated circuit.
BACKGROUND
Many of today's integrated circuit (IC) designs are a complete system on a chip (SOC) that include a processor core, multiple embedded memories, logic, I/O ports, etc. Embedded memories are the densest components within a SOC, accounting for up to 90% of the chip area. Memories are also the most sensitive to manufacturing process defects, making it essential to thoroughly test them in a SOC.
As ICs are produced with greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test cost and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high-fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms.
There are generally three approaches to testing of embedded memories. One technique is to use automatic test equipment (ATE) that is located external to the circuit under test and that applies test patterns stored in the ATE.
FIG. 1
is a block diagram of a conventional system
18
for testing digital circuits with scan chains. External ATE
20
applies a set of fully specified test patterns
22
one by one to a circuit under test
24
in scan mode via scan chains
26
within the circuit. The circuit is then run in normal mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the responses are routed to the tester
20
, which compares the response with the fault free reference response
28
. This approach is advantageous because there are a wide variety of test algorithms that can be used and the algorithms can easily be changed in the ATE. However, as the complexity of circuits continues to increase, the ATE approach to testing embedded memories has become increasingly difficult. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. Fourth, present external testing equipment is unable to test such larger circuits at their speed of operation, unless prohibitively expensive ATEs are used. Testing at the speed of operation allows for the detection of timing faults that might otherwise be undetected at slower speeds. This is particularly significant for memories that operate at very high speed.
Another technique for testing of embedded memories is to use an embedded CPU. Using an embedded CPU is advantageous because no additional testing hardware is needed and the test algorithms can be easily modified. However, the CPU does not always have access to all of the memories on the integrated circuit. Additionally, it is difficult to automate the process to program the CPU for generation of the memory test algorithms. Finally, it is very difficult to test the memories that store the memory test program itself.
The third approach to testing embedded memories is to use Built-in self-test (BIST) techniques. BIST has become the most popular method for testing embedded memories. To use this method, one or more BIST controllers are inserted within the SOC during the chip's design using a software design tool. The chip is then fabricated with the added BIST controllers. During testing of the fabricated chip, a BIST controller is instructed to supply a series of patterns to the ports of an embedded memory. These patterns, also called test algorithms, typically include, but are not limited to, march-type and checkerboard-type patterns that cause a memory to produce deterministic output data. The output data can be directly compared with reference data from the BIST controller. The comparison generates a signal indicating that the memory passed or failed the test.
Unfortunately, BIST requires additional hardware overhead and there is a performance penalty of BIST controllers and access logic. However, as memory sizes continue to increase, the hardware overhead is becoming relatively small. There are several advantages to BIST. The BIST circuitry generates a wide variety of memory test algorithms to achieve a high quality test. Additionally, BIST provides diagnostic resolution down to one memory cell. Finally, BIST can operate with a very low cost ATE.
FIG. 2
shows a prior art BIST designed for testing embedded memories. A BIST controller
30
includes a finite state machine
32
and control, data, and address registers
34
-
36
, respectively, for reading and writing data to a memory
38
. Other logic, shown generally at
40
, represents the core logic that performs the IC's functions during normal operation. Multiplexers
42
are used to switch the IC from a test mode (where the BIST controller
30
controls the memory
38
) to an operational mode (where the logic
40
reads and writes memory
38
). In the test mode, compare circuitry
44
is used to compare values read from memory
38
to reference data
46
stored in the BIST controller
30
. Once the compare is completed, the compare circuitry
44
is responsive to a compare capture register
48
in the BIST controller to output the resulting data, which indicates whether the read passed or failed. Although not shown, a clock controls both the BIST controller and the memories being tested so that the two are synchronized. Also, although only one memory is shown in
FIG. 2
, typically, a BIST controller tests multiple memories.
FIG. 3A
shows a timing diagram for a read operation of the circuit of FIG.
2
. The read operation takes three clock cycles to complete. During a first clock cycle, the control and address registers
34
,
36
of the BIST controller
30
are set up for a read operation. This typically includes storing an address of the desired memory element in the address register
36
and setting the control register
34
for a read operation. On the next clock cycle, the memory outputs the data to the compare circuitry
44
. During this cycle, the compare circuitry compares the value read from memory with the reference data supplied from register
46
. The compare circuitry
44
then determines whether the reference data matched (passed) the memory data or whether it did not match (failed). On a third clock cycle, the compare circuitry
44
outputs the pass/fail signal as controlled by the compare capture register
48
. After the first read is completed, a second read begins that requires three additional clock cycles.
FIG. 3B
shows a write operation for the circuitry of FIG.
2
. The write operation requires two clock cycles. During a first clock cycle, the BIST controller
30
stores the address of the desired memory location in the address register
36
. The BIST controller also stores the data to be written in the data register
35
and places the control register
34
in the proper configuration for a memory write. On the next clock cycle, the memory writes the data from data register
35
to the memory addressed by the address register
36
. Every subsequent write operation requires two additional clock cycles.
There are several problems with the prior art test circuitry of FIG.
2
. Foremost, the read operation requires three clock cycles to complete and a write requires two cycles to complete. In normal operation, the memory can run much faster. As a result, some timing faults may go undetected. Additionally, the overall testing time is extremely long because of the long read and write cycles. As memory sizes continue to increase, overall testing time will also increase.
Thus, there is a need for a test circuit that tests memory at full-speed and that requires less overall test time to complete a memor

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