Full memory chip long write test mode

Details Full memory chip long write test mode Full memory chip long write test mode

1994-09-30

1996-03-26

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365154, 36523003, 365156, 371 211, G11C 2900

Patent

active

055026788

ABSTRACT:
According to the present invention, a first memory block of the memory chip is placed into the long write test mode, meaning that all wordlines of the first memory block are turned off and the voltages on all the bitlines of the first memory block are controlled such that either all the bitlines true of a memory block are equal to a low logic level, all the bitlines complement of the memory block are equal to the low logic level, or all the bitlines true and bitlines complement of the memory block are both equal to the low logic level. Next, a second memory block of the memory chip is likewise placed into the long write test mode, while the first memory block remains in the long write test mode. After a long pause which causes a long write disturb condition, the memory blocks of the memory chip are one by one taken out of the long write test and read disturbed. Then, the rows of the first memory block are selected, one by one, in minimal cycle time to read disturb the first memory block. Next, the second memory block of the memory chip is likewise placed into the read disturb mode, while the first memory block is deselected and thus not affected.

REFERENCES:
patent: 5255230 (1993-10-01), Chan et al.
Test of Random-Access Memory, IBM Technical Disclosure Bulletin, vol. 29 No. 8 Jan. 1987, pp. 3622-3625.

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