Full face mask for capacitance-voltage measurements

Stock material or miscellaneous articles – Structurally defined web or sheet – Including aperture

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Details

428131, 428134, 428135, 428136, 428192, 118505, 118721, 20429811, C23C 1434, B32B 324

Patent

active

060964049

ABSTRACT:
A mask for covering a substrate for performing capacitance-voltage measurements on the substrate is a full-faced mask covering substantially all of the substrate and having a thin outer section and a thicker inner section, so that the outer section is thin enough to permit desired clearance tolerances when inserting the substrate/mask assembly into or removing it from a cassette, and the inner section is thick enough to provide structural stability to the mask to ensure proper contact between the mask and the test substrate. The mask may include a ring with one or more strips across the ring with holes in the strips for target material deposition. In an alternative embodiment, the mask may be a disk with holes at various locations across the disk. In either embodiment, the mask generally conforms to the shape of the substrate, so that the clamp ring of the PVD chamber seats on the mask or on the substrate, so little or none of the plasma or sputtered material can escape between the substrate and clamp ring. Various embodiments of the mask provide different ways to hold the mask on the substrate, such as clamping with clips, gluing with an adhesive, folding extensions of the mask over the edge of the substrate, and holding by surface tension.

REFERENCES:
patent: 4704306 (1987-11-01), Nakamura
patent: 4830723 (1989-05-01), Galvagni et al.
patent: 4988424 (1991-01-01), Woodward et al.
patent: 5154797 (1992-10-01), Blomquist et al.
patent: 5223108 (1993-06-01), Hurwitt
patent: 5338424 (1994-08-01), Drimer et al.
patent: 5393398 (1995-02-01), Sugano
patent: 5863396 (1999-01-01), Flanigan

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