Full CMOS SRAM cell comprising Vcc and Vss buses on both sides o

Details Full CMOS SRAM cell comprising Vcc and Vss buses on both sides o Full CMOS SRAM cell comprising Vcc and Vss buses on both sides o

1997-07-11

2000-12-12

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257903, H01L 2976, H01L 2711

Patent

active

061602981

ABSTRACT:
According to a novel pattern layout of a full CMOS SRAM cell comprising first and second transfer, driver, and load transistors, six in total, the driver and load transistors are parallel to a buried word line. The first transfer transistor and the first driver transistor are alongside and parallel to one complementary data line and the second transfer transistor and the second driver transistor are alongside and parallel to the other complementary data line. Moreover, a power bus and a reference bus are parallel to and on both sides of each of the complementary data lines. Preferably, four gate electrodes of the first and second driver and load transistors are individually formed while the word line is used gate electrodes of the first and second transfer transistors.

REFERENCES:
patent: 4481524 (1984-11-01), Tsujide
patent: 5083178 (1992-01-01), Otsu
patent: 5818089 (1998-10-01), Kokubo et al.
Uehara et al, "A Novel Local Interconnect Technology (MSD) for High-Performance Logic LSIs with Embedded SRAM", IEEE, 1996, p. 142-3.
Ueshima et al, A 5-.mu.m.sup.2 Full-CMOS Cell for High-Speed SRAMs Utilizing a Optical-Proximity-Effect Correction (OPC) Technology, IEEE, 1996, p. 146-7.
1996 Symposium on VLSI Technology, Digest of Technical Papers, IEEE, 1996, p. ix.
Sekiyama et al, "A 1-V Operating 256-kb Full-CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, p. 776-782.

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