Full CMOS SRAM cell

Details Full CMOS SRAM cell Full CMOS SRAM cell

2000-12-01

2002-09-03

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S202000, C257S206000, C257S211000, C257S909000

Reexamination Certificate

active

06445017

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a full complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell.
2. Description of the Related Art
An SRAM semiconductor memory device has a lower power consumption and a higher operation speed than a dynamic random access memory (DRAM). Thus, the SRAM device is widely used for cache memory of computer and portable electronic devices.
A memory cell of the SRAM device is divided into two types of cells, that is, one is a high load resistor cell employing a high load resistor as a load device, and the other is a CMOS type cell employing a PMOS transistor as a load device.
The CMOS type cell is also divided into two types of cells, that is, one is a thin-film transistor (TFT) cell employing a thin-film transistor (TFT) as the load device, and the other is a full CMOS cell employing a bulk transistor as the load device.
FIG. 1
is an equivalent circuit diagram of a general CMOS SRAM cell. Referring to
FIG. 1
, the CMOS SRAM cell is formed of a pair of driver transistors TD
1
and TD
2
, a pair of transfer transistors TA
1
and TA
2
, and a pair of load transistors TL
1
and TL
2
. Here, the pair of driver transistors TD
1
and TD
2
, and the pair of transfer transistors TA
1
and TA
2
are NMOS transistors. The pair of load transistors TL
1
and TL
2
are PMOS transistors.
A first driver transistor TD
1
and a first transfer transistor TA
1
are connected in series with each other. A source area of the first driver transistor TD
1
is connected to a ground line Vss, and a drain area of the first transfer transistor TA
1
is connected to a first bit line BL. Similarly, a second driver transistor TD
2
and a second transfer transistor TA
2
are also connected in series with each other. Also, a source area of the second driver transistor TD
2
is connected to the ground line Vss, and a drain area of the second transfer transistor TA
2
is connected to a second bit line /BL. The first and second bit lines BL and /BL maintain opposite information.
A source area and a drain area of a first load transistor TL
1
are connected to a power line Vcc and a drain area of the first driver transistor TD
1
, namely, a first node N
1
, respectively. Similarly, a source area and a drain area of a second load transistor TL
2
are connected to the power line Vcc and a drain area of the second driver transistor TD
2
, namely, a second node N
2
, respectively. A gate electrode of the first driver transistor TD
1
and a gate electrode of the first load transistor TL
1
are connected to the second node N
2
, and a gate electrode of the second driver transistor TD
2
and a gate electrode of the second load transistor TL
2
are connected to the first node N
1
. Also, gate electrodes of the first and second transfer transistors TA
1
and TA
2
are connected to a word line WL.
The above-described CMOS cell shows a lower stand-by current and a higher noise margin than a load resistor cell. Thus, the CMOS cell is widely used for a high-performance SRAM device requiring a low power supply voltage.
The equivalent circuit of the CMOS SRAM cell shown in
FIG. 1
can be implemented on a semiconductor substrate in many configurations.
FIG. 2
is a layout diagram of a conventional SRAM cell for implementing the equivalent circuit of the CMOS SRAM cell shown in
FIG. 1
on the semiconductor substrate, and is one of many layout diagrams of an SRAM cell disclosed in a paper published by M. Ishida et al. (M. Ishida et al., IEDM 98, pp. 201-204). Also, M. Ishida et al. discloses the same cell layout diagram as that of the invention disclosed in the U.S. Pat. No. 5,654,915.
Referring to
FIG. 2
, a n-well region
21
is formed in a predetermined area of the semiconductor substrate, and an U-shaped first active region
23
a
is arranged in a p-well region around the n-well region
21
. A second active region
23
b
parallel to an x-axis is arranged in the n-well region
21
. A word line
25
w
is arranged on the semiconductor substrate so as to intersect the first active region
23
a
. The word line
25
w
is arranged parallel to the X-axis and intersects two parts of the first active region
23
a
. A first common gate electrode
25
a
intersecting the first active region
23
a
and the second active region
23
b
is arranged parallel to a y-axis. Also, a second common gate electrode
25
b
intersecting the first and second active regions
23
a
and
23
b
is arranged parallel to the y-axis. As a result, a pair of transfer transistors TA
1
and TA
2
and a pair of driver transistors TD
1
and TD
2
, in which the word line
25
w
, the first common gate electrode
25
a
and the second common gate electrode
25
b
function as the gate electrode, are formed in the first active region
23
a
. Similarly, a pair of load transistors TL
1
and TL
2
, in which the first common gate electrode
25
a
and the second common gate electrode
25
b
function as the gate electrode, are formed in the second active region
23
b
. As a result, the first driver transistor TD
1
and the first load transistor TL
1
form a first inverter, and the second driver transistor TD
2
and the second load transistor TL
2
form a second inverter.
A first node contact
27
a
is arranged on a drain area of the second driver transistor TD
2
(an active region shared by the second driver transistor TD
2
and the second transfer transistor TA
2
), a drain area of the second load transistor TL
2
, and the first common gate electrode
25
a
to expos them. And, a second node contact
27
b
is arranged on a drain area of the first driver transistor TD
1
(an active region shared by the first driver transistor TD
1
and the first transfer transistor TA
1
), a drain area of the first load transistor TL
1
, and the second common gate electrode
25
b
to expose them. Also, a ground contact
28
s
is arranged on the first active region
23
a
(a common source area of the first and second driver transistors TD
1
and TD
2
) between the first common gate electrode
25
a
and the second common gate electrode
25
b
to expose itself. And, a power contact
28
c
is arranged on the second active region
23
b
(a common source area of the first and second load transistors TL
1
and TL
2
) between the first common gate electrode
25
a
and the second common gate electrode
25
b
to expose itself. Further, first and second bit line contacts
29
a
and
29
b
are arranged on the first active region
23
a
adjacent to the word line
25
w
to expose itself.
The conventional full CMOS SRAM cell shown in
FIG. 2
may be very sensitive to misarrangement during a photo process. Also, it is easy for leakage current to be caused in a node contact of the SRAM cell of FIG.
2
.
FIG. 3
is a plan view of patterns in which the layout view of
FIG. 2
is projected on the semiconductor substrate. Referring to
FIG. 3
, corner portions of actual active regions
23
a
′ and
23
b
′ formed after a photo process are transformed into a round shape. In particular, the first active region
23
a
of
FIG. 2
has two curved regions C and C′, which are curved by 90°. Thus, it is easy for crystalline defects to be caused in the semiconductor substrate around the curved regions C and C′. This is the reason why stress or damage from etching is concentrically applied to the curved regions while active regions are formed. In other words, this is the reason why stress from a pad nitride layer or damage from etching a trench is concentrated on the curved regions C and C′, and as a result, it is easy for crystalline defects to be caused in the semiconductor substrate when a device isolation layer defining the active regions is formed by a local oxidation of silicon (LOCOS) process or a trench process. As a result, if the first and second node contacts (
27
a
and
27
b
of
FIG. 2
) are formed in the curved regions C and C′ in the following process, a leakage current flowing through each of the node contacts incr

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