Full CMOS slew rate controlled input/output buffer

Details Full CMOS slew rate controlled input/output buffer Full CMOS slew rate controlled input/output buffer

1998-12-04

2000-12-12

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 87, 326 27, 326 83, H03K 190185

Patent

active

06160416&

ABSTRACT:
An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node. In one preferred method, the current is injected or taken by controlling a first driving circuit so as to inject a current into the output node or controlling a second driving circuit so as to take a current from the output node.

REFERENCES:
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patent: 5717343 (1998-02-01), Kwong
patent: 5789937 (1998-08-01), Cao et al.
patent: 5877647 (1999-03-01), Vajapey et al.
patent: 5914618 (1999-06-01), Mattos

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