Static information storage and retrieval – Read/write circuit – Serial read/write
Patent
1995-12-14
1997-05-06
Hudspeth, David R.
Static information storage and retrieval
Read/write circuit
Serial read/write
36518917, 326 46, 326 93, H03K 1901
Patent
active
056277970
ABSTRACT:
The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.
REFERENCES:
patent: 4839866 (1989-06-01), Ward et al.
patent: 5305253 (1994-04-01), Ward
patent: 5406554 (1995-04-01), Parry
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5513318 (1996-04-01), Van De Goor et al.
patent: 5521876 (1996-05-01), Hattori et al.
Hawkins Andrew L.
Narayana Pidugu L.
Cypress Semiconductor Corporation
Hudspeth David R.
LandOfFree
Full and empty flag generator for synchronous FIFOS does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Full and empty flag generator for synchronous FIFOS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Full and empty flag generator for synchronous FIFOS will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2137903