Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1996-06-11
1999-10-05
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 46, 326 93, 365221, H03K 1900
Patent
active
059630566
ABSTRACT:
The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.
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Hawkins Andrew L.
Narayana Pidugu L.
Cypress Semiconductor Corp.
Maiorana Christopher P.
Santamauro Jon
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