Frontside contact on silicon-on-insulator substrate

Details Frontside contact on silicon-on-insulator substrate Frontside contact on silicon-on-insulator substrate

2001-11-27

2003-08-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S149000, C438S152000, C438S243000, C438S717000

Reexamination Certificate

active

06603166

ABSTRACT:

FIELD
The present invention relates generally to device processing of Silicon-On-Insulator (SOI) wafers, and more particularly, relates to a method of forming a frontside contact to the silicon substrate of a SOI wafer.
BACKGROUND
SOI is a device processing technique that places an insulating layer (e.g. a buried oxide layer) over the silicon substrate. Transistors are then fabricated in a layer of silicon located on top of the insulating layer. This technique may provide higher speeds and use less power by reducing capacitance, making device operation on SOI superior to the conventional Complementary Metal-Oxide Semiconductor (CMOS) techniques.
In many applications it is desirable to ground or bias the silicon substrate of an SOI circuit. However, in most of the more advanced packaging technologies, such as flip chip and die stacking, making a connection to the substrate is cost prohibitive. Therefore, connecting the substrate to a frontside contact is necessary. The standard semiconductor manufacturing process must typically be modified to make this frontside contact.
Submicron lithography requires a high degree of planarity in the contact dielectric to define the contact and metal interconnect layers. In order to make simultaneous contact to the gate polysilicon, the source/drain regions, and the underlying substrate, the selectivity requirements must be increased significantly to be able to etch the planarized contact dielectric down to the silicon substrate. These requirements increase the cost of manufacturing.
A frontside contact formation process was described by Brady, et al. in U.S. Pat. No. 5,314,841, “Method of Forming a Frontside Contact to the Silicon Substrate of a SOI Wafer.” This process forms a frontside contact without planarization of the structure as seen in FIG.
1
. This requires significant adjustment of the contact etch to be compatible with today's planarized contact dielectric processes.
U.S. patent application Ser. No. 09/163,687, titled “Method for Forming a Frontside Contact to the Silicon Substrate of a SOI Wafer in the Presence of Planarized Contact Dielectrics,” which is assigned to the same assignee as the present invention, describes another technique for forming such a contact. This technique includes a positive profile and a local interconnect as seen in FIG.
2
. The positive profile impacts density, while the local interconnect is not required for all SOI processes.
The techniques and structures disclosed herein are believed to improve upon these prior attempts.
SUMMARY
Exemplary embodiments are described for connecting a silicon substrate layer of an SOI wafer to a frontside contact. A hole is etched through a field oxide layer and a buried oxide layer, exposing the silicon substrate layer in the area in which the frontside contact is to be formed. An implant is performed in the silicon substrate layer in the area of the hole. Connection polysilicon is then deposited in the hole and etched to form the frontside contact. A contact dielectric layer is then deposited. A contact hole is etched into the contact dielectric layer and filled with a refractory metal forming a contact plug. A metal pad is then located above the contact plug to provide surface wiring to other components on the wafer. Placing doped spacers in the hole prior to depositing the connection polysilicon can provide additional doping.


REFERENCES:
patent: 5049521 (1991-09-01), Belanger et al.
patent: 5314841 (1994-05-01), Brady et al.
patent: 5569621 (1996-10-01), Yallup et al.
patent: 5610083 (1997-03-01), Chan et al.
patent: 6300666 (2001-10-01), Fechner et al.
patent: 6355511 (2002-03-01), Lukanc et al.
patent: 2 346 260 (2000-08-01), None
patent: 9 153468 (1997-06-01), None
U.S. patent application Ser. No. 09/163,687, Fechner et al., filed Sep. 30, 1998.

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