Pulse or digital communications – Spread spectrum – Frequency hopping
Reexamination Certificate
1999-08-30
2003-09-16
Vo, Don N. (Department: 2631)
Pulse or digital communications
Spread spectrum
Frequency hopping
C455S076000
Reexamination Certificate
active
06621853
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to mobile communication systems, and in particular, to a device and method for providing a fast lock time by hopping an intermediate frequency and a radio frequency.
2. Description of the Related Art
In general, radio communication systems include a frequency synthesizer having a phase locked loop (PLL). In a GMPCS (Global Mobile Personal Communication by Satellite) system, such as, iridium, global star and ICO (Intermediate Circuit Orbit), for example, the frequency synthesizer uses a dual frequency band frequency synthesizer. The frequency synthesizer used in the GMPCS system has a dual PLL which generates a radio local oscillating frequency and an intermediate local oscillating frequency. These two frequencies are used to convert an input signal frequency into a desired carrier frequency fc.
A frequency synthesizer typically comprises a reference oscillator, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and a programmable counter.
In the dual PLL, a fractional N counter is used for the radio local oscillating frequency, and an integer N counter is used for the intermediate local oscillating frequency. The integer N counter consists of P (prescaler), B and A (programmable) counters satisfying the following equation N=P×B+A (where P, B and A are all integers). The fractional N counter includes an F (fractional) counter in addition to the P, B and A counters, satisfying the following equation N=P×B+A+F (where P, B and A are all integers, P, A, and F is a fractional number less than 1).
A frequency synthesizer having a general dual PLL construction uses a frequency division multiple access (FDMA) technique where each user is assigned a different frequency. To assign a frequency per channel (i.e., user) in the FDMA technique, the integer N counter and fractional N counter operate by 24-bit control data provided from a baseband circuit. The integer N counter provides a uniform frequency without frequency hopping under control of the baseband circuit to output one intermediate local oscillating frequency. The fractional N counter outputs a radio local oscillating frequency hopping in increments of a prescribed frequency according to the channel.
For example, in a transmitter of an ICO system, an intermediate local oscillating frequency of 430.0 MHZ is demultiplied by ½ and thus a 215.0 MHZ signal is applied to a mixer as an input representing the uniform frequency without frequency hopping. One of a number of radio local oscillating frequencies of (2200+0.025×n) MHZ are spaced at 25 kHz increments is also applied to the mixer as another input. Therefore, the output of the mixer, that is, an ICO transmitting frequency is the difference of the two inputs, namely, {(2200+0.025×n)−215}MHZ=(1985+0.025×n) MHZ, where n is an integral number, i.e., 1, 2, 3, 4, . . . , its bandwidth being 25 KHz. In a receiver of the ICO, the intermediate local oscillating frequency is preferably fixed at 456.0 MHZ and the radio local oscillating frequency is sequentially incremented (or hopped) in units of 25 KHz.
For a GMPCS system, the radio local oscillating frequency should be some multiple of 25 KHz because the frequency bandwidth of the GMPCS system is 25 KHz. If the radio local oscillating frequency is a multiple of 25 KHz, a phase detector of a PLL used for radio local oscillation should also use 25 KHz as a comparison frequency. Since the PLL used for radio local oscillation employs a fractional N counter with modulus−16, the maximum comparison frequency of the phase detector is 400 KHz (=25 KHz×16). The comparison frequency is an important factor in determining a lock time in designing a system, whereby the lock time becomes faster as the comparison frequency is increased. Generally, the GMPCS system has 1199 channels and a demanded lock time of 350 Fs. The more channels the system has, the faster the demanded lock time. A high comparison frequency is desirable to obtain a fast lock time.
As described above, it is difficult to flexibly change the comparison frequency to a desired frequency band (i.e., higher frequency), so it is impossible to achieve a faster lock time. Namely, since the intermediate local oscillating frequency is fixed, the comparison frequency range is limited to, for example, 25 KHz (mod. 16/16), 50 KHz (mod. 8/16), 100 KHz (mod. 4/16) and 400 KHz (mod.1/16). Also, the lock time and phase noise are influenced by the comparison frequency. However, since the range of generating the comparison frequency is restricted, it is difficult to provide a fast lock time.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a dual frequency hopping device and method for a frequency synthesizer, in which an intermediate local oscillating frequency hops per channel in increments defined by a first prescribed frequency, and a radio local oscillating frequency hops in increments defined by a second prescribed frequency only after the intermediate local oscillating frequency reaches a target frequency, thereby fully utilizing an RF channel band.
In accordance with one embodiment of the present invention, a dual-frequency hopping method for a frequency synthesizer having a dual phase locked loop includes the steps of decreasing an intermediate local oscillating frequency in increments defined by a first prescribed frequency a prescribed number of times as a channel is sequentially increased, to output an intermediate local oscillating frequency signal, and increasing a radio local oscillating frequency by one level in units of a second prescribed frequency after the intermediate local oscillating frequency has been decreased the prescribed number of times, to output a radio local oscillating frequency signal.
In accordance with a second embodiment of the present invention, a dual-frequency hopping device for a frequency synthesizer having a baseband processor and a reference frequency generator are provided for generating a reference frequency signal under control of the baseband processor. The dual-frequency hopping device further includes an intermediate frequency local oscillator for demultiplying the reference frequency signal and decreasing an intermediate local oscillating frequency a prescribed number of times in increments of a first prescribed frequency as a channel is sequentially increased, and a radio frequency local oscillator for demultiplying the reference frequency and increasing a radio local oscillating frequency in increments of a second prescribed frequency after the intermediate local oscillating frequency has been decreased the prescribed number of times.
REFERENCES:
patent: 6009313 (1999-12-01), Ichiyoshi
patent: 6028850 (2000-02-01), Kang
patent: 6061575 (2000-05-01), Lombardi
Dilworth & Barrese LLP
Nguyen Dung X
Samsung Electronics Co,. Ltd.
Vo Don N.
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