Frequency synthesizer with improved priority channel switching

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 17, 331 25, H03L 700

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045595054

ABSTRACT:
A frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pair of alternatingly connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.

REFERENCES:
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patent: 3617895 (1971-11-01), Tomsa
patent: 3729688 (1973-04-01), Cerny, Jr. et al.
patent: 3750032 (1982-07-01), Andrews
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patent: 4243941 (1981-01-01), Zdunek
patent: 4330758 (1982-05-01), Swisher et al.
Rhodes, R. et al., "Frequency Agile Phase-Locked Loop Synthesizer for a Communications Satellite", NTC '80, Houston, Tex., Nov. 3,-Dec. 4, 1980.
IEEE National Telecommunications Conference, 1980, pp. 22.3.1-22.3.6.
Josefsberg, Y., "Stable and Fast PLL Switches Loop Bandwidths", Electronics, Mar. 10, 1982, p. 139.

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