Frequency synthesizer with constant loop characteristics

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

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331 25, 327156, 327157, H03L 718

Patent

active

061373680

ABSTRACT:
A frequency synthesizer is provided. The synthesizer includes a phase detector for receiving an input signal and a feedback signal and for generating a phase error signal corresponding to a difference between the input signal and the feedback signal. A charge pump generates a charge pump signal having a polarity controlled by the phase error signal. A variable oscillator generates an oscillation signal in response to the charge pump signal. A first frequency divider divides a frequency of the oscillation signal by a first divisor to produce a first divided output signal as an output signal of said frequency synthesizer. A second frequency divider divides a frequency of the first divided output signal by a second divisor to produce the feedback signal. A loop adjustor adjusts the first signal divisor in response to the second signal divisor or adjusts the second signal divisor in response to the first signal divisor. The adjustment is performed so as to constantly maintain the product of the first divisor and the second divisor. The present invention allows for the PLL loop characteristics to remain unchanged. Moreover, since loop characteristics remain unchanged, additional circuitry is not required to adjust the loop characteristics.

REFERENCES:
patent: 3769602 (1973-10-01), Griswold
patent: 3890619 (1975-06-01), Mounce
patent: 4862109 (1989-08-01), Cowley
patent: 5710526 (1998-01-01), Nauta et al.
patent: 5832375 (1998-11-01), Leisten et al.

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