Frequency synthesizer and frequency synthesis method

Details Frequency synthesizer and frequency synthesis method Frequency synthesizer and frequency synthesis method

2005-08-17

2008-09-09

Jackson, Blane J (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S076000, C455S260000, C331S034000, C331S00100A

Reexamination Certificate

active

07424280

ABSTRACT:
A dual frequency synthesizer includes a reference oscillator, an R counter, a first fractional-N phase-locked loop (for a receiving channel) and a second fractional-N phase-locked loop (for a transmitting channel) and one shared sigma-delta modulator. The reference oscillator outputs a reference oscillation frequency clock. The R counter outputs a reference frequency clock based on the reference oscillation frequency clock. The first fractional-N phase-locked loop (PLL) (for a receiving channel) generates a first (receiving channel frequency) clock based on the reference frequency clock. The second fractional-N phase-locked loop (for a transmitting channel) generates a second (transmitting channel frequency) clock based on the same reference frequency clock. Both fractional-N phase-locked loops share a common sigma-delta modulator. Therefore, the chip size of the dual frequency synthesizer may be reduced.

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