Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-12-14
2004-10-19
Liu, Shuwang (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C375S327000
Reexamination Certificate
active
06807244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency synthesizer and, more particularly, to a device that can control the frequency of output clocks with high precision.
2. Related Background Art
FIG. 21
is a schematic block diagram showing the arrangement of a conventional frequency synthesizer.
A frequency dividing circuit
110
frequency-divides a reference clock signal Kr having a frequency fr by a fixed frequency dividing value Nr, and supplies the frequency division result to a phase comparison circuit
112
as a reference signal R. A control signal generation circuit
116
supplies a driving control signal to a voltage controlled oscillator
118
, which oscillates at a frequency fv corresponding to that driving control signal. An output signal Kv having the frequency fv is externally output, and is also supplied to a variable frequency dividing circuit
120
. The variable frequency dividing circuit
120
frequency-divides the output from the voltage controlled oscillator
118
by a frequency dividing value Nv, and supplies the frequency division result to the phase comparison circuit
112
as a comparison signal V. The frequency division value Nv can be freely changed by frequency division value setting data DF. When the comparison signal V lags behind the reference signal R (or leads it), the phase comparison circuit
112
supplies an up pulse U (or down pulse D) to a charge pump circuit
114
. The charge pump circuit
114
generates an error voltage based on the up or down pulse U or D, and supplies it to the control signal generation circuit
116
. The control signal generation circuit
116
generates a driving control signal which sets the comparison signal V in phase with the reference signal R, and supplies it to the voltage controlled oscillator
118
.
In the circuit shown in
FIG. 21
, the following relation holds:
fv
=(
Nv/Nr
)×
fr
In this way, the circuit shown in
FIG. 21
outputs a clock signal Kv having the frequency fv, which is obtained by multiplying the reference clock frequency fr by a coefficient.
In general, such frequency synthesizer is designed based on th variable frequency range and frequency setting precision. For example, assume that the variable frequency range is ±1,500 ppm or higher, and the frequency setting precision is around 15 ppm. In this case, since
½{circumflex over ( )}16=1/65536=15.25 ppm
((65536/(65536-128))-1)*10
6
=+1957 ppm
((65536-256)/(65536-128)-1)*10
6
=−1957 ppm
an example of the variable frequency dividing circuit
120
can be designed as follows. That is,
the number of counter bits: 16 bits
frequency division value setting data DF: 8 bits
frequency division value range: 65280 to 65536.
However, the conventional circuit suffers the following problems.
That is, when the frequency setting precision is to be improved, the frequency division value of the variable frequency dividing circuit
120
must be increased. This means that the frequency check intervals of the output signal Kv become large, and the voltage controlled oscillator
118
must hold an oscillating frequency over several ten thousand clocks in accordance with the improved frequency setting precision.
However, a voltage controlled oscillator that can maintain stable frequency over several ten thousand clocks cannot be easily realized by only a conventional versatile LSI process, and cannot be manufactured with low cost.
When such clock generation circuit is mounted in a color laser print engine, no stable operation is guaranteed in a pixel modulation circuit formed as a system LSI.
In order to stably hold an oscillating frequency in accordance with the improved frequency setting precision, the oscillation output signal must be stably controlled by not only the voltage controlled oscillator
118
but also a charge pump circuit
114
that uses a large-size capacitor which cannot be implemented by an LSI, at the cost of attack/recovery performance.
However, when attack/recovery performance is sacrificed to stably control the oscillation output signal by the charge pump circuit
114
, quick output frequency switching cannot be done, resulting in a limited application range.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the aforementioned problems.
It is another object of the present invention to provide a frequency synthesize which can attain high-precision frequency control and can be formed as an LSI using a low-cost arrangement.
It is still another object of the present invention to allow to change the image position and size with high precision.
In order to achieve the above objects, according to one aspect of the present invention, there is provided a frequency synthesizer for generating an output signal having a frequency which is associated with a frequency of a reference clock, comprising:
oscillating means for generating a clock signal group including a plurality of clock signals which have a phase difference associated with a period of the output signal;
comparison clock generation means for generating a comparison clock by selectively using the plurality of clock signals;
phase difference detection means for detecting a phase difference between the reference clock and the comparison clock; and
frequency control means for controlling an oscillating frequency of the oscillating means in accordance with an output from the phase difference detection means.
The above and other objects and features of the present invention will become apparent from the following detailed description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5448193 (1995-09-01), Baumert et al.
patent: 6081905 (2000-06-01), Larsson et al.
patent: 6373911 (2002-04-01), Tajima et al.
patent: 6563888 (2003-05-01), Toriyama
Kawano Fujio
Kawasaki Somei
Canon Kabushiki Kaisha
Cowan Liebowitz & Latman
Liu Shuwang
Wang Ted
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