Frequency synthesiser

Details Frequency synthesiser Frequency synthesiser

1999-06-03

2001-10-02

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C455S076000, C455S260000, C332S127000, C327S159000

Reexamination Certificate

active

06298106

ABSTRACT:

OBJECT OF THE INVENTION
The present invention relates to a frequency synthesizer. More specifically, the present invention relates to a frequency synthesizer with a non-integer, fractional relationship between the input signal frequency and the output signal frequency, that is, the respective input and output frequencies are not multiples of each other.
STATE OF THE ART
With reference to
FIG. 1
, the patent U.S. Pat. No. 5,267,189 describes a fractional frequency synthesiser comprising two dividers
10
and
12
and a PLL (phase locked loop)
11
. The input reference signal Sr is applied to a first input of the PLL
11
through the frequency divider
10
. A second input of the PLL receives the output signal of the PLL
11
through the frequency divider
12
. The PLL
11
comprises typically a phase comparator, a filter and a voltage controlled oscillator, or equivalent circuits of the type described in the patent U.S. Pat. No. 5,267,189, incorporated in this application by reference. The comparator compares the phases of the two output signals from the dividers
10
and
12
, respectively, in order to produce a control signal that is applied to an input of the voltage controlled oscillator, VCO, through the filter. The purpose of the comparator in the PLL is to correct the frequency difference between the frequency of the output signal of the divider
12
and the frequency of the output signal of the divider
10
. The result being that if F is the frequency of the reference signal and if M and N are the division coefficients of the dividers
10
and
12
, respectively, the output signal So has a frequency F×(N/M).
With reference to
FIG. 1
, the patent U.S. Pat. No. 5,267,189 describes a fractional frequency synthesizer comprising two dividers
10
and
12
and a PLL (phase locked loop)
11
. The input reference signal Sr is applied to a first input of the PLL
11
through the frequency divider
10
. A second input of the PLL receives the output signal of the PLL
11
through the frequency divider
12
. The PLL
11
comprises typically a phase comparator, a filter and a voltage controlled oscillator, or equivalent circuits of the type described in the patent U.S. Pat. No. 5,267,189, incorporated in this application by reference. The comparator compares the phases of the two output signals from the dividers
10
and
12
, respectively, in order to produce a control signal that is applied to an input of the voltage controlled oscillator, VCO, through the filter. The purpose of the comparator in the PLL is to correct the frequency difference between the frequency of the output signal of the divider
12
and the frequency of the output signal of the divider
10
. The result being that if F is the frequency of the reference signal and if M and N are the division coefficients of the dividers
10
and
12
, respectively, the output signal So has a frequency F×(N/M).
CHARACTERIZATION OF THE INVENTION
A first object of the present invention is to provide a frequency synthesizer with a non-integer fractional relationship between the input signal frequency and the output signal frequency, capable of being incorporated into an integrated circuit.
A second object of the present invention is to obtain a synthesizer with an instantaneous phase shift as small as possible, that is, each of the periods of the resulting signal at the output of the synthesizer shall have a duration as close as possible to their nominal value, satisfying the condition that the sum of the duration of a certain number of consecutive periods be equal to that of the same number of nominal periods.
Consequently, a synthesizer for generating a digital output signal the frequency of which has a fractional relationship of value Nn/Nd, where Nn and Nd are integers numbers, with respect to the frequency of a digital input signal, is characterized in that it comprises a frequency multiplier to multiply by M, where M is an integer number, the input signal frequency in order to generate a high frequency intermediate signal and means to divide by (M×Nd)/Nn the frequency of this intermediate signal in order to generate said output signal.
The process of multiplying the input signal frequency by M and subsequently dividing the resulting signal frequency by (M×Nd)/Nn permits very restricted phase fluctuations in the output signal from the synthesiser without the need to have a very selective filter in the PLL. There are certain applications that tolerate clock generation having this phase uncertainty in the output signal.
For example, the frequency multiplier comprises a PLL the first input of which receives the input signal and the output of which is applied to a second input of the PLL through a modulus M frequency divider.
According to a first embodiment, M is such that (M×Nd)/Nn is an integer number.


REFERENCES:
patent: 4516083 (1985-05-01), Turney
patent: 4573023 (1986-02-01), Cok et al.
patent: 5815042 (1998-09-01), Chow et al.
patent: 6005904 (1999-12-01), Knapp et al.
patent: 6066990 (2000-05-01), Genest
patent: 6081164 (2000-06-01), Shigemori et al.

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