Electronic digital logic circuitry – Exclusive function
Patent
1994-12-23
1997-03-25
Westin, Edward P.
Electronic digital logic circuitry
Exclusive function
326 54, 326 55, 326 17, 327116, H03K 1921
Patent
active
056148410
ABSTRACT:
The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.
REFERENCES:
patent: 3252011 (1966-05-01), Zuk
patent: 3993957 (1976-11-01), Davenport
patent: 4367420 (1983-01-01), Foss et al.
patent: 4507574 (1985-03-01), Seki et al.
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 5120989 (1992-06-01), Johnson et al.
patent: 5448181 (1995-09-01), Chiang
IBM Technical Disclosure Bulletin, vol. 32, No. 7 Dec. 1989, pp. 464-467, "Fast Parity Tree" entire document.
Proceedings of 32nd Midwest Symposium on Circuits and Systems, Aug. 14-16, 1989, Chancellor Hotel and Conven--et al: "On CMOS Exclusive OR Design", FIG. 1A.
IEEE Transactions on Computers, vol. 42, No. 2, Feb. 1993, New York, US, pp. 179-189, Niraj K. Jha: "Fault Detection in CVS Parity Trees with Application of Strongly Self-Checking Parity and Two-Rail Checkers", FIG. 4.
IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 990-991; I. Hernandez, Jr.: "Frequency Multiplier Using Delay Circuit" entire document.
Streetman, Ben G.; "Solid State Electronic Devices, 2nd Edition"; .COPYRGT.1980 by Prentice-Hall; p. 443.
Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective"; .COPYRGT.1985 by AT&T Bell Laboratories, Inc. & Kamran Eahraghian; pp. 18183 & 196-201.
IBM Technical Disclosure Bulletin; published anonymously; vol. 30, No. 4; Sep. 1987; pp. 1480-1481.
Cofler Andrew
Le Bihan Jean-Claude
Marbot Roland
Nezamzadeh-Moosavi Reza
Bull S.A.
Driscoll Benjamin D.
Kondracki Edward J.
Westin Edward P.
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