Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-12-27
1999-02-09
Chin, Wellington
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375354, 375375, 370503, 370517, H04L 700
Patent
active
058704450
ABSTRACT:
A clock distribution system including a variable delay circuit responsive to a reference clock signal having a fixed clock pulse width and a variable clock period for providing a delayed clock signal, an inverter for inverting the delayed clock signal to an inverted delayed clock signal, a clock tree for providing multiple replicas of the inverted delayed clock signal, a comparator responsive to the reference clock signal and a selected one of the multiple replicas of the inverted delayed clock signal for controlling the variable delay circuit such that the selected replica is delayed by one clock pulse width relative to the reference clock signal. Also disclosed is a shift register controlled variable delay line that can be implemented in the variable delay circuit.
REFERENCES:
patent: 5223755 (1993-06-01), Richley
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5604775 (1997-02-01), Saitoh et al.
Alkov Leonard A.
Chin Wellington
Lenzen, Jr. Glenn H.
Raytheon Company
Tran Congvan
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